[mips][microMIPS] Extending size reduction pass with LWP and SWP

Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Differential Revision: https://reviews.llvm.org/D39115

llvm-svn: 334595

9 files changed, 583 insertions, 18 deletions

diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
index 7cc6fbb2a7a..cc361367001 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
@@ -335,8 +335,7 @@ define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
 ;
 ; MM32R3-LABEL: and_i128:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    lw $3, 20($sp)
-; MM32R3-NEXT:    lw $2, 16($sp)
+; MM32R3-NEXT:    lwp $2, 16($sp)
 ; MM32R3-NEXT:    and16 $2, $4
 ; MM32R3-NEXT:    and16 $3, $5
 ; MM32R3-NEXT:    lw $4, 24($sp)
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index 140f545f239..dc19c9e81a9 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -791,8 +791,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
 ; MMR3:       # %bb.0: # %entry
 ; MMR3-NEXT:    addiusp -48
 ; MMR3-NEXT:    .cfi_def_cfa_offset 48
-; MMR3-NEXT:    sw $17, 44($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    sw $16, 40($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    swp $16, 40($sp)
 ; MMR3-NEXT:    .cfi_offset 17, -4
 ; MMR3-NEXT:    .cfi_offset 16, -8
 ; MMR3-NEXT:    move $8, $7
@@ -870,8 +869,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
 ; MMR3-NEXT:    movn $2, $11, $10
 ; MMR3-NEXT:    move $3, $8
 ; MMR3-NEXT:    move $4, $1
-; MMR3-NEXT:    lw $16, 40($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    lw $17, 44($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    lwp $16, 40($sp)
 ; MMR3-NEXT:    addiusp 48
 ; MMR3-NEXT:    jrc $ra
 ;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index 5f18295cd63..80682409a68 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -818,8 +818,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
 ; MMR3:       # %bb.0: # %entry
 ; MMR3-NEXT:    addiusp -40
 ; MMR3-NEXT:    .cfi_def_cfa_offset 40
-; MMR3-NEXT:    sw $17, 36($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    sw $16, 32($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    swp $16, 32($sp)
 ; MMR3-NEXT:    .cfi_offset 17, -4
 ; MMR3-NEXT:    .cfi_offset 16, -8
 ; MMR3-NEXT:    move $8, $7
@@ -896,8 +895,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
 ; MMR3-NEXT:    li16 $4, 0
 ; MMR3-NEXT:    movz $2, $4, $10
 ; MMR3-NEXT:    move $4, $1
-; MMR3-NEXT:    lw $16, 32($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    lw $17, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    lwp $16, 32($sp)
 ; MMR3-NEXT:    addiusp 40
 ; MMR3-NEXT:    jrc $ra
 ;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/or.ll b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
index 7f9998e449c..ce22f08385b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
@@ -176,8 +176,7 @@ define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
 ;
 ; MM32-LABEL: or_i128:
 ; MM32:       # %bb.0: # %entry
-; MM32-NEXT:    lw $3, 20($sp)
-; MM32-NEXT:    lw $2, 16($sp)
+; MM32-NEXT:    lwp $2, 16($sp)
 ; MM32-NEXT:    or16 $2, $4
 ; MM32-NEXT:    or16 $3, $5
 ; MM32-NEXT:    lw $4, 24($sp)
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
index a6a635dac39..6c34f63cf06 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -847,8 +847,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
 ; MMR3:       # %bb.0: # %entry
 ; MMR3-NEXT:    addiusp -40
 ; MMR3-NEXT:    .cfi_def_cfa_offset 40
-; MMR3-NEXT:    sw $17, 36($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    sw $16, 32($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    swp $16, 32($sp)
 ; MMR3-NEXT:    .cfi_offset 17, -4
 ; MMR3-NEXT:    .cfi_offset 16, -8
 ; MMR3-NEXT:    move $17, $7
@@ -926,8 +925,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
 ; MMR3-NEXT:    movz $6, $3, $10
 ; MMR3-NEXT:    move $3, $8
 ; MMR3-NEXT:    move $5, $6
-; MMR3-NEXT:    lw $16, 32($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    lw $17, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    lwp $16, 32($sp)
 ; MMR3-NEXT:    addiusp 40
 ; MMR3-NEXT:    jrc $ra
 ;
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
index 48291f868a2..54bb179b117 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -333,8 +333,7 @@ define signext i128 @xor_i128(i128 signext %a, i128 signext %b) {
 ;
 ; MM32R3-LABEL: xor_i128:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    lw $3, 20($sp)
-; MM32R3-NEXT:    lw $2, 16($sp)
+; MM32R3-NEXT:    lwp $2, 16($sp)
 ; MM32R3-NEXT:    xor16 $2, $4
 ; MM32R3-NEXT:    xor16 $3, $5
 ; MM32R3-NEXT:    lw $4, 24($sp)
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.ll
new file mode 100644
index 00000000000..9481f32e17f
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mattr=+micromips -mcpu=mips32r2 \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define i32 @fun(i32* %adr, i32 %val) {
+; CHECK-LABEL: fun:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiusp -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    sw $ra, 28($sp) # 4-byte Folded Spill
+; CHECK-NEXT:    swp $16, 20($sp)
+; CHECK-NEXT:    .cfi_offset 31, -4
+; CHECK-NEXT:    .cfi_offset 17, -8
+; CHECK-NEXT:    .cfi_offset 16, -12
+; CHECK-NEXT:    move $17, $5
+; CHECK-NEXT:    move $16, $4
+; CHECK-NEXT:    jal fun1
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    sw16 $17, 0($16)
+; CHECK-NEXT:    li16 $2, 0
+; CHECK-NEXT:    lwp $16, 20($sp)
+; CHECK-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addiusp 32
+; CHECK-NEXT:    jrc $ra
+entry:
+  %call1 =  call i32* @fun1()
+  store i32 %val, i32* %adr, align 4
+  ret i32 0
+}
+
+declare i32* @fun1()
+
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
new file mode 100644
index 00000000000..a23e3337a54
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
@@ -0,0 +1,289 @@
+# RUN: llc -mtriple=mipsel-unknown-linux-gnu -mattr=+micromips -mcpu=mips32r2 \
+# RUN:     -verify-machineinstrs -run-pass micromips-reduce-size \
+# RUN:      %s -o - | FileCheck %s
+
+--- |
+  define void @f1(i32* %adr, i32 %val) { ret void }
+  define void @f2(i32* %adr, i32 %val) { ret void }
+  define void @f3(i32* %adr, i32 %val) { ret void }
+  define void @f4(i32* %adr, i32 %val) { ret void }
+
+  declare i32* @f()
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**)
+
+...
+---
+# CHECK-LABEL: name: f1
+# CHECK: SWP_MM
+# CHECK: LWP_MM
+name:            f1
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a0', virtual-reg: '' }
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       32
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s1', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a0, $a1, $ra, $s1, $s0
+
+    $sp = ADDiu $sp, -32
+    CFI_INSTRUCTION def_cfa_offset 32
+    SW killed $ra, $sp, 28 :: (store 4 into %stack.0)
+    SW killed $s1, $sp, 24 :: (store 4 into %stack.1)
+    SW killed $s0, $sp, 20 :: (store 4 into %stack.2)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s1_64, -8
+    CFI_INSTRUCTION offset $s0_64, -12
+    $s1 = MOVE16_MM $a1
+    $s0 = MOVE16_MM $a0
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store 4 into %ir.adr)
+    $v0 = LI16_MM 0
+    $s0 = LW $sp, 20 :: (load 4 from %stack.2)
+    $s1 = LW $sp, 24 :: (load 4 from %stack.1)
+    $ra = LW $sp, 28 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 32
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+# CHECK-LABEL: name: f2
+# CHECK: SWP_MM
+# CHECK: LWP_MM
+name:            f2
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a0', virtual-reg: '' }
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       32
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s1', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a0, $a1, $ra, $s1, $s0
+
+    $sp = ADDiu $sp, -32
+    CFI_INSTRUCTION def_cfa_offset 32
+    SW killed $ra, $sp, 28 :: (store 4 into %stack.0)
+    SW_MM killed $s1, $sp, 24 :: (store 4 into %stack.1)
+    SW_MM killed $s0, $sp, 20 :: (store 4 into %stack.2)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s1_64, -8
+    CFI_INSTRUCTION offset $s0_64, -12
+    $s1 = MOVE16_MM $a1
+    $s0 = MOVE16_MM $a0
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store 4 into %ir.adr)
+    $v0 = LI16_MM 0
+    $s0 = LW_MM $sp, 20 :: (load 4 from %stack.2)
+    $s1 = LW_MM $sp, 24 :: (load 4 from %stack.1)
+    $ra = LW $sp, 28 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 32
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+# CHECK-LABEL: name: f3
+# CHECK: SWP_MM
+# CHECK: LWP_MM
+name:            f3
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a0', virtual-reg: '' }
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       32
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s1', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a0, $a1, $ra, $s1, $s0
+
+    $sp = ADDiu $sp, -32
+    CFI_INSTRUCTION def_cfa_offset 32
+    SW killed $ra, $sp, 28 :: (store 4 into %stack.0)
+    SW_MM killed $s1, $sp, 24 :: (store 4 into %stack.1)
+    SW killed $s0, $sp, 20 :: (store 4 into %stack.2)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s1_64, -8
+    CFI_INSTRUCTION offset $s0_64, -12
+    $s1 = MOVE16_MM $a1
+    $s0 = MOVE16_MM $a0
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store 4 into %ir.adr)
+    $v0 = LI16_MM 0
+    $s0 = LW_MM $sp, 20 :: (load 4 from %stack.2)
+    $s1 = LW $sp, 24 :: (load 4 from %stack.1)
+    $ra = LW $sp, 28 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 32
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+# CHECK-LABEL: name: f4
+# CHECK: SWP_MM
+# CHECK: LWP_MM
+name:            f4
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a0', virtual-reg: '' }
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       32
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s1', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a0, $a1, $ra, $s1, $s0
+
+    $sp = ADDiu $sp, -32
+    CFI_INSTRUCTION def_cfa_offset 32
+    SW killed $ra, $sp, 28 :: (store 4 into %stack.0)
+    SW killed $s1, $sp, 24 :: (store 4 into %stack.1)
+    SW_MM killed $s0, $sp, 20 :: (store 4 into %stack.2)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s1_64, -8
+    CFI_INSTRUCTION offset $s0_64, -12
+    $s1 = MOVE16_MM $a1
+    $s0 = MOVE16_MM $a0
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    SW16_MM killed renamable $s1, killed renamable $s0, 0 :: (store 4 into %ir.adr)
+    $v0 = LI16_MM 0
+    $s0 = LW $sp, 20 :: (load 4 from %stack.2)
+    $s1 = LW_MM $sp, 24 :: (load 4 from %stack.1)
+    $ra = LW $sp, 28 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 32
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
new file mode 100644
index 00000000000..a38b08265f9
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
@@ -0,0 +1,252 @@
+# RUN: llc -mtriple=mipsel-unknown-linux-gnu -mattr=+micromips -mcpu=mips32r2 \
+# RUN:     -verify-machineinstrs -run-pass micromips-reduce-size \
+# RUN:      %s -o - | FileCheck %s
+
+--- |
+  define void @f1(i32* %adr, i32 %val) { ret void }
+  define void @f2(i32* %adr, i32 %val) { ret void }
+  define void @f3(i32* %adr, i32 %val) { ret void }
+  define void @f4(i32* %adr, i32 %val) { ret void }
+
+  declare i32* @f()
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**)
+...
+---
+# CHECK-LABEL: name: f1
+# CHECK-NOT: SWP_MM
+# CHECK-NOT: LWP_MM
+name:            f1
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a1, $ra, $s0
+
+    $sp = ADDiu $sp, -24
+    CFI_INSTRUCTION def_cfa_offset 24
+    SW killed $ra, $sp, 20 :: (store 4 into %stack.0)
+    SW killed $s0, $sp, 16 :: (store 4 into %stack.1)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s0_64, -8
+    $s0 = MOVE16_MM $a1
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    $v0 = MOVE16_MM killed $s0
+    $s0 = LW $sp, 16 :: (load 4 from %stack.1)
+    $ra = LW $sp, 20 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 24
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+# CHECK-LABEL: name: f2
+# CHECK-NOT: SWP_MM
+# CHECK-NOT: LWP_MM
+name:            f2
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a1, $ra, $s0
+
+    $sp = ADDiu $sp, -24
+    CFI_INSTRUCTION def_cfa_offset 24
+    SW_MM killed $ra, $sp, 20 :: (store 4 into %stack.0)
+    SW_MM killed $s0, $sp, 16 :: (store 4 into %stack.1)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s0_64, -8
+    $s0 = MOVE16_MM $a1
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    $v0 = MOVE16_MM killed $s0
+    $s0 = LW_MM $sp, 16 :: (load 4 from %stack.1)
+    $ra = LW_MM $sp, 20 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 24
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+# CHECK-LABEL: name: f3
+# CHECK-NOT: SWP_MM
+# CHECK-NOT: LWP_MM
+name:            f3
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a1, $ra, $s0
+
+    $sp = ADDiu $sp, -24
+    CFI_INSTRUCTION def_cfa_offset 24
+    SW_MM killed $ra, $sp, 20 :: (store 4 into %stack.0)
+    SW killed $s0, $sp, 16 :: (store 4 into %stack.1)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s0_64, -8
+    $s0 = MOVE16_MM $a1
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    $v0 = MOVE16_MM killed $s0
+    $s0 = LW_MM $sp, 16 :: (load 4 from %stack.1)
+    $ra = LW $sp, 20 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 24
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+---
+# CHECK-LABEL: name: f4
+# CHECK-NOT: SWP_MM
+# CHECK-NOT: LWP_MM
+name:            f4
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$a1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 16
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0:
+    liveins: $a1, $ra, $s0
+
+    $sp = ADDiu $sp, -24
+    CFI_INSTRUCTION def_cfa_offset 24
+    SW killed $ra, $sp, 20 :: (store 4 into %stack.0)
+    SW_MM killed $s0, $sp, 16 :: (store 4 into %stack.1)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s0_64, -8
+    $s0 = MOVE16_MM $a1
+    JAL @f, csr_o32, implicit-def dead $ra, implicit-def $sp, implicit-def dead $v0
+    $v0 = MOVE16_MM killed $s0
+    $s0 = LW $sp, 16 :: (load 4 from %stack.1)
+    $ra = LW_MM $sp, 20 :: (load 4 from %stack.0)
+    $sp = ADDiu $sp, 24
+    PseudoReturn undef $ra, implicit killed $v0
+
+...
+