diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2011-10-07 16:15:08 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2011-10-07 16:15:08 +0000 |
| commit | 318d6bae80b72b4572281d4c066ca7caa86b1eb5 (patch) | |
| tree | edfb4fceb3eb471e108279eeb279c0529a91f012 /llvm/test | |
| parent | e19661e0ca5ac59545554d283bb62a75d6700ce4 (diff) | |
| download | bcm5719-llvm-318d6bae80b72b4572281d4c066ca7caa86b1eb5.tar.gz bcm5719-llvm-318d6bae80b72b4572281d4c066ca7caa86b1eb5.zip | |
Peephole optimization for ABS on ARM.
Patch by Ana Pazos!
llvm-svn: 141365
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/iabs.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb/iabs.ll | 11 |
2 files changed, 12 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/ARM/iabs.ll b/llvm/test/CodeGen/ARM/iabs.ll index c01c041cfe8..89e309d1606 100644 --- a/llvm/test/CodeGen/ARM/iabs.ll +++ b/llvm/test/CodeGen/ARM/iabs.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s ;; Integer absolute value, should produce something as good as: ARM: -;; add r3, r0, r0, asr #31 -;; eor r0, r3, r0, asr #31 +;; movs r0, r0 +;; rsbmi r0, r0, #0 ;; bx lr define i32 @test(i32 %a) { @@ -10,7 +10,7 @@ define i32 @test(i32 %a) { %b = icmp sgt i32 %a, -1 %abs = select i1 %b, i32 %a, i32 %tmp1neg ret i32 %abs -; CHECK: add r1, r0, r0, asr #31 -; CHECK: eor r0, r1, r0, asr #31 +; CHECK: movs r0, r0 +; CHECK: rsbmi r0, r0, #0 ; CHECK: bx lr } diff --git a/llvm/test/CodeGen/Thumb/iabs.ll b/llvm/test/CodeGen/Thumb/iabs.ll index d7cdcd8149a..d03b5b2e3be 100644 --- a/llvm/test/CodeGen/Thumb/iabs.ll +++ b/llvm/test/CodeGen/Thumb/iabs.ll @@ -3,9 +3,9 @@ ;; Integer absolute value, should produce something as good as: ;; Thumb: -;; asr r2, r0, #31 -;; add r0, r0, r2 -;; eor r0, r2 +;; movs r0, r0 +;; bpl +;; rsb r0, r0, #0 (with opitmization, bpl + rsb is if-converted into rsbmi) ;; bx lr define i32 @test(i32 %a) { @@ -13,5 +13,10 @@ define i32 @test(i32 %a) { %b = icmp sgt i32 %a, -1 %abs = select i1 %b, i32 %a, i32 %tmp1neg ret i32 %abs +; CHECK: movs r0, r0 +; CHECK: bpl +; CHECK: rsb r0, r0, #0 +; CHECK: bx lr } + |
