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| author | Craig Topper <craig.topper@intel.com> | 2018-09-07 02:39:56 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-09-07 02:39:56 +0000 |
| commit | 30e129f2562951a82ec25a32da8be8b535649c38 (patch) | |
| tree | 052563c463b9be2721662141c2933dabbebffb4d /llvm/test | |
| parent | 2ccb31977c87081a668c11938a2e34cbf9d1abca (diff) | |
| download | bcm5719-llvm-30e129f2562951a82ec25a32da8be8b535649c38.tar.gz bcm5719-llvm-30e129f2562951a82ec25a32da8be8b535649c38.zip | |
[X86] Add more test cases for missed opportunities for using RMW form of ADC.
llvm-svn: 341630
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/addcarry.ll | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll index 159da9b1928..7037072f88f 100644 --- a/llvm/test/CodeGen/X86/addcarry.ll +++ b/llvm/test/CodeGen/X86/addcarry.ll @@ -59,6 +59,39 @@ entry: ret i256 %0 } +define void @add256_rmw(i256* %a, i256 %b) nounwind { +; CHECK-LABEL: add256_rmw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq %rsi, (%rdi) +; CHECK-NEXT: adcq %rdx, 8(%rdi) +; CHECK-NEXT: adcq %rcx, 16(%rdi) +; CHECK-NEXT: adcq %r8, 24(%rdi) +; CHECK-NEXT: retq +entry: + %0 = load i256, i256* %a + %1 = add i256 %0, %b + store i256 %1, i256* %a + ret void +} + +define void @add256_rmw2(i256 %a, i256* %b) nounwind { +; CHECK-LABEL: add256_rmw2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addq (%r8), %rdi +; CHECK-NEXT: adcq 8(%r8), %rsi +; CHECK-NEXT: adcq 16(%r8), %rdx +; CHECK-NEXT: adcq %rcx, 24(%r8) +; CHECK-NEXT: movq %rdi, (%r8) +; CHECK-NEXT: movq %rsi, 8(%r8) +; CHECK-NEXT: movq %rdx, 16(%r8) +; CHECK-NEXT: retq +entry: + %0 = load i256, i256* %b + %1 = add i256 %a, %0 + store i256 %1, i256* %b + ret void +} + define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind { ; CHECK-LABEL: a: ; CHECK: # %bb.0: # %entry |
