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| author | Austin Kerbow <Austin.Kerbow@amd.com> | 2019-10-18 18:20:30 +0000 |
|---|---|---|
| committer | Austin Kerbow <Austin.Kerbow@amd.com> | 2019-10-18 18:20:30 +0000 |
| commit | 2f41a023afdb68364ea490135874425e85faa574 (patch) | |
| tree | d6336ec578fe85973fe719263c7adcfa4d03e65c /llvm/test | |
| parent | 80873de5323884d942cf23c0164a6cc932e9ab7e (diff) | |
| download | bcm5719-llvm-2f41a023afdb68364ea490135874425e85faa574.tar.gz bcm5719-llvm-2f41a023afdb68364ea490135874425e85faa574.zip | |
AMDGPU: Fix SMEM WAR hazard for gfx10 readlane
Summary: Hazard recognizer fails to see hazard with V_READLANE_B32_gfx10.
Reviewers: rampitec
Reviewed By: rampitec
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69172
llvm-svn: 375265
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir b/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir index 0796754ddf9..531cca11e47 100644 --- a/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir +++ b/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir @@ -304,6 +304,21 @@ body: | S_ENDPGM 0 ... +# Workaround since spilling/restoring SGPRs use real opcodes. +# GCN-LABEL: name: hazard_smem_war_readlane_gfx10 +# GCN: S_LOAD_DWORD_IMM +# GCN: $sgpr_null = S_MOV_B32 0 +# GCN-NEXT: V_READLANE_B32_gfx10 +--- +name: hazard_smem_war_readlane_gfx10 +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0 + $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0 + $sgpr0 = V_READLANE_B32_gfx10 $vgpr0, $sgpr3 + S_ENDPGM 0 +... + # GCN-LABEL: name: hazard_smem_war_readfirstlane # GCN: S_LOAD_DWORD_IMM # GCN: $sgpr_null = S_MOV_B32 0 |
