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| author | Sanjay Patel <spatel@rotateright.com> | 2017-06-25 14:15:28 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2017-06-25 14:15:28 +0000 |
| commit | 2f3ead7adc103ac855ef739f9b6782df138db233 (patch) | |
| tree | 92bdcceac3604c3853742fa4a19ea376aa236519 /llvm/test | |
| parent | 72f991cdedeeabc72d00b3d79ecc55a3a025dd81 (diff) | |
| download | bcm5719-llvm-2f3ead7adc103ac855ef739f9b6782df138db233.tar.gz bcm5719-llvm-2f3ead7adc103ac855ef739f9b6782df138db233.zip | |
[InstCombine] add (sext i1 X), 1 --> zext (not X)
http://rise4fun.com/Alive/i8Q
A narrow bitwise logic op is obviously better than math for value tracking,
and zext is better than sext. Typically, the 'not' will be folded into an
icmp predicate.
The IR difference would even survive through codegen for x86, so we would see
worse code:
https://godbolt.org/g/C14HMF
one_or_zero(int, int): # @one_or_zero(int, int)
xorl %eax, %eax
cmpl %esi, %edi
setle %al
retq
one_or_zero_alt(int, int): # @one_or_zero_alt(int, int)
xorl %ecx, %ecx
cmpl %esi, %edi
setg %cl
movl $1, %eax
subl %ecx, %eax
retq
llvm-svn: 306243
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/add.ll | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll index 5f7101e8fec..9cc2ae4fcb0 100644 --- a/llvm/test/Transforms/InstCombine/add.ll +++ b/llvm/test/Transforms/InstCombine/add.ll @@ -1,12 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s -; TODO: This should be canonicalized to either a select or xor+zext. - define i32 @select_0_or_1_from_bool(i1 %x) { ; CHECK-LABEL: @select_0_or_1_from_bool( -; CHECK-NEXT: [[EXT:%.*]] = sext i1 %x to i32 -; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[EXT]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = xor i1 %x, true +; CHECK-NEXT: [[ADD:%.*]] = zext i1 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[ADD]] ; %ext = sext i1 %x to i32 @@ -14,12 +12,10 @@ define i32 @select_0_or_1_from_bool(i1 %x) { ret i32 %add } -; TODO: This should be canonicalized to either a select or xor+zext. - define <2 x i32> @select_0_or_1_from_bool_vec(<2 x i1> %x) { ; CHECK-LABEL: @select_0_or_1_from_bool_vec( -; CHECK-NEXT: [[EXT:%.*]] = sext <2 x i1> %x to <2 x i32> -; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i32> [[EXT]], <i32 1, i32 1> +; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i1> %x, <i1 true, i1 true> +; CHECK-NEXT: [[ADD:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[ADD]] ; %ext = sext <2 x i1> %x to <2 x i32> |
