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| author | Alex Lorenz <arphaman@gmail.com> | 2015-07-13 23:24:34 +0000 |
|---|---|---|
| committer | Alex Lorenz <arphaman@gmail.com> | 2015-07-13 23:24:34 +0000 |
| commit | 2eacca86ef2c255bae8eff43056dfa6c57ae7092 (patch) | |
| tree | 7cf5e2db8512f3ba90e733e02829b93793a19b7c /llvm/test | |
| parent | 8c1a9102e620e436b12df5b8c28d90e41aff17ce (diff) | |
| download | bcm5719-llvm-2eacca86ef2c255bae8eff43056dfa6c57ae7092.tar.gz bcm5719-llvm-2eacca86ef2c255bae8eff43056dfa6c57ae7092.zip | |
MIR Serialization: Serialize the sub register indices.
This commit serializes the sub register indices from the register machine
operands.
Reviewers: Duncan P. N. Exon Smith
llvm-svn: 242084
Diffstat (limited to 'llvm/test')
3 files changed, 93 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir new file mode 100644 index 00000000000..c891a115a18 --- /dev/null +++ b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir @@ -0,0 +1,29 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define zeroext i1 @t(i1 %c) { + entry: + ret i1 %c + } + +... +--- +name: t +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr8 } + - { id: 2, class: gr8 } +body: + - name: entry + id: 0 + instructions: + - '%0 = COPY %edi' + # CHECK: [[@LINE+1]]:25: expected a subregister index after ':' + - '%1 = COPY %0 : 42' + - '%2 = AND8ri %1, 1, implicit-def %eflags' + - '%al = COPY %2' + - 'RETQ %al' +... diff --git a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir new file mode 100644 index 00000000000..5e46fab4b05 --- /dev/null +++ b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir @@ -0,0 +1,33 @@ +# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses subregisters in register operands +# correctly. + +--- | + + define zeroext i1 @t(i1 %c) { + entry: + ret i1 %c + } + +... +--- +name: t +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr8 } + - { id: 2, class: gr8 } +body: + - name: entry + id: 0 + instructions: + # CHECK: %0 = COPY %edi + # CHECK-NEXT: %1 = COPY %0:sub_8bit + - '%0 = COPY %edi' + - '%1 = COPY %0:sub_8bit' + - '%2 = AND8ri %1, 1, implicit-def %eflags' + - '%al = COPY %2' + - 'RETQ %al' +... + diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir new file mode 100644 index 00000000000..50461232b62 --- /dev/null +++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir @@ -0,0 +1,31 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an unknown subregister index +# is encountered. + +--- | + + define zeroext i1 @t(i1 %c) { + entry: + ret i1 %c + } + +... +--- +name: t +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr8 } + - { id: 2, class: gr8 } +body: + - name: entry + id: 0 + instructions: + - '%0 = COPY %edi' + # CHECK: [[@LINE+1]]:23: use of unknown subregister index 'bit8' + - '%1 = COPY %0:bit8' + - '%2 = AND8ri %1, 1, implicit-def %eflags' + - '%al = COPY %2' + - 'RETQ %al' +... |
