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| author | Matthias Braun <matze@braunis.de> | 2016-12-09 19:08:15 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-12-09 19:08:15 +0000 |
| commit | 2c7d52a5407ad7145629a8d089b3aa59547a158f (patch) | |
| tree | 5bc66a6a14dcc3cea0b8e9e56b30299d4028dda4 /llvm/test | |
| parent | 3bdc0f165b2a7a950918ee0f26925b74e028a61a (diff) | |
| download | bcm5719-llvm-2c7d52a5407ad7145629a8d089b3aa59547a158f.tar.gz bcm5719-llvm-2c7d52a5407ad7145629a8d089b3aa59547a158f.zip | |
Move .mir tests to appropriate directories
test/CodeGen/MIR should contain tests that intent to test the MIR
printing or parsing. Tests that test something else should be in
test/CodeGen/TargetName even when they are written in .mir.
As a rule of thumb, only tests using "llc -run-pass none" should be in
test/CodeGen/MIR.
llvm-svn: 289254
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir (renamed from llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/machine-dead-copy.mir (renamed from llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/machine-scheduler.mir (renamed from llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/machine-sink-zr.mir (renamed from llvm/test/CodeGen/MIR/AArch64/machine-sink-zr.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/insert-waits-exp.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/insert-waits-exp.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/invert-br-undef-vcc.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/liveness.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/liveness.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/movrels-bug.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/movrels-bug.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/optimize-if-exec-masking.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/subreg-intervals.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/vccz-corrupt-bug-workaround.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/waitcnt.mir (renamed from llvm/test/CodeGen/MIR/AMDGPU/waitcnt.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/imm-peephole-arm.mir (renamed from llvm/test/CodeGen/MIR/ARM/imm-peephole-arm.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/imm-peephole-thumb.mir (renamed from llvm/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/anti-dep-partial.mir (renamed from llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Lanai/peephole-compare.mir (renamed from llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir) | 0 | ||||
| -rw-r--r-- | llvm/test/CodeGen/MIR/Lanai/lit.local.cfg | 2 |
23 files changed, 0 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir b/llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir index 75ad849e4f3..75ad849e4f3 100644 --- a/llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir b/llvm/test/CodeGen/AArch64/machine-dead-copy.mir index cb552e5cab3..cb552e5cab3 100644 --- a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir +++ b/llvm/test/CodeGen/AArch64/machine-dead-copy.mir diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir b/llvm/test/CodeGen/AArch64/machine-scheduler.mir index e7e0dda53c5..e7e0dda53c5 100644 --- a/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir +++ b/llvm/test/CodeGen/AArch64/machine-scheduler.mir diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-sink-zr.mir b/llvm/test/CodeGen/AArch64/machine-sink-zr.mir index 535fba0dc63..535fba0dc63 100644 --- a/llvm/test/CodeGen/MIR/AArch64/machine-sink-zr.mir +++ b/llvm/test/CodeGen/AArch64/machine-sink-zr.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir index 234fe57b513..234fe57b513 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir index 9d70f67ef49..9d70f67ef49 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir +++ b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/insert-waits-exp.mir b/llvm/test/CodeGen/AMDGPU/insert-waits-exp.mir index 9aaa374ed28..9aaa374ed28 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/insert-waits-exp.mir +++ b/llvm/test/CodeGen/AMDGPU/insert-waits-exp.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir index 7cc9c7c1d92..7cc9c7c1d92 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir +++ b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invert-br-undef-vcc.mir b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir index 66182d09289..66182d09289 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/invert-br-undef-vcc.mir +++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/liveness.mir b/llvm/test/CodeGen/AMDGPU/liveness.mir index 112c3f8e69a..112c3f8e69a 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/liveness.mir +++ b/llvm/test/CodeGen/AMDGPU/liveness.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/movrels-bug.mir b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir index 9c330bc8a6b..9c330bc8a6b 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/movrels-bug.mir +++ b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/optimize-if-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir index 4584802ad5a..4584802ad5a 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/optimize-if-exec-masking.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir index b928bc7086b..b928bc7086b 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir b/llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir index af71086e542..af71086e542 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir +++ b/llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir index 0c08deb13a8..0c08deb13a8 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir index c4e00215159..c4e00215159 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir +++ b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/vccz-corrupt-bug-workaround.mir b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir index 03e473e3a0c..03e473e3a0c 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/vccz-corrupt-bug-workaround.mir +++ b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir diff --git a/llvm/test/CodeGen/MIR/AMDGPU/waitcnt.mir b/llvm/test/CodeGen/AMDGPU/waitcnt.mir index cb5de6a2419..cb5de6a2419 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/waitcnt.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt.mir diff --git a/llvm/test/CodeGen/MIR/ARM/imm-peephole-arm.mir b/llvm/test/CodeGen/ARM/imm-peephole-arm.mir index cd30bdb74d5..cd30bdb74d5 100644 --- a/llvm/test/CodeGen/MIR/ARM/imm-peephole-arm.mir +++ b/llvm/test/CodeGen/ARM/imm-peephole-arm.mir diff --git a/llvm/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir b/llvm/test/CodeGen/ARM/imm-peephole-thumb.mir index 3d342902d80..3d342902d80 100644 --- a/llvm/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir +++ b/llvm/test/CodeGen/ARM/imm-peephole-thumb.mir diff --git a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir b/llvm/test/CodeGen/Hexagon/anti-dep-partial.mir index 09bc49c508a..09bc49c508a 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir +++ b/llvm/test/CodeGen/Hexagon/anti-dep-partial.mir diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/Lanai/peephole-compare.mir index 5056a05ed1f..5056a05ed1f 100644 --- a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir +++ b/llvm/test/CodeGen/Lanai/peephole-compare.mir diff --git a/llvm/test/CodeGen/MIR/Lanai/lit.local.cfg b/llvm/test/CodeGen/MIR/Lanai/lit.local.cfg deleted file mode 100644 index f1b8b4f4e21..00000000000 --- a/llvm/test/CodeGen/MIR/Lanai/lit.local.cfg +++ /dev/null @@ -1,2 +0,0 @@ -if not 'Lanai' in config.root.targets: - config.unsupported = True |
