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author | Craig Topper <craig.topper@gmail.com> | 2016-12-18 04:17:00 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2016-12-18 04:17:00 +0000 |
commit | 2baef8f466447d8621be9e8bfbb6b14e7baba2a4 (patch) | |
tree | db027155ffed0449bb7ce354864a7c5a3b143db3 /llvm/test | |
parent | 1d3dcb0602df7a1f641bd02352c72e16c0c76485 (diff) | |
download | bcm5719-llvm-2baef8f466447d8621be9e8bfbb6b14e7baba2a4.tar.gz bcm5719-llvm-2baef8f466447d8621be9e8bfbb6b14e7baba2a4.zip |
[AVX-512] Make sure VLX is also enabled before using EVEX encoded logic ops for scalars. I missed this in r290049.
llvm-svn: 290055
Diffstat (limited to 'llvm/test')
-rw-r--r-- | llvm/test/CodeGen/X86/fp-logic-replace.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/fp-logic-replace.ll b/llvm/test/CodeGen/X86/fp-logic-replace.ll index 628e99f8859..ac3da445ed6 100644 --- a/llvm/test/CodeGen/X86/fp-logic-replace.ll +++ b/llvm/test/CodeGen/X86/fp-logic-replace.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+sse2 | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx | FileCheck %s --check-prefix=AVX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq | FileCheck %s --check-prefix=AVX512DQ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=AVX512DQ ; Test that we can replace "scalar" FP-bitwise-logic with the optimal instruction. ; Scalar x86 FP-logic instructions only exist in your imagination and/or the bowels |