[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction

This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction.

Differential Revision: https://reviews.llvm.org/D48918

llvm-svn: 336418

7 files changed, 84 insertions, 0 deletions

diff --git a/llvm/test/MC/AArch64/armv8.4a-trace-error.s b/llvm/test/MC/AArch64/armv8.4a-trace-error.s
new file mode 100644
index 00000000000..99b61280a31
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.4a-trace-error.s
@@ -0,0 +1,23 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A Debug, Trace and PMU Extensions
+//------------------------------------------------------------------------------
+
+tsb
+tsb foo
+tsb #0
+tsb 0
+
+//CHECK-ERROR: error: too few operands for instruction
+//CHECK-ERROR: tsb
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: 'csync' operand expected
+//CHECK-ERROR: tsb foo
+//CHECK-ERROR:     ^
+//CHECK-ERROR: error: 'csync' operand expected
+//CHECK-ERROR: tsb #0
+//CHECK-ERROR:     ^
+//CHECK-ERROR: error: 'csync' operand expected
+//CHECK-ERROR: tsb 0
+//CHECK-ERROR:     ^
diff --git a/llvm/test/MC/AArch64/armv8.4a-trace.s b/llvm/test/MC/AArch64/armv8.4a-trace.s
index c11b80ddf04..d14b0e0ef7e 100644
--- a/llvm/test/MC/AArch64/armv8.4a-trace.s
+++ b/llvm/test/MC/AArch64/armv8.4a-trace.s
@@ -13,6 +13,8 @@ mrs x0, TRFCR_EL1
 mrs x0, TRFCR_EL2
 mrs x0, TRFCR_EL12
 
+tsb csync
+
 //CHECK:  msr TRFCR_EL1, x0           // encoding: [0x20,0x12,0x18,0xd5]
 //CHECK:  msr TRFCR_EL2, x0           // encoding: [0x20,0x12,0x1c,0xd5]
 //CHECK:  msr TRFCR_EL12, x0          // encoding: [0x20,0x12,0x1d,0xd5]
@@ -21,6 +23,8 @@ mrs x0, TRFCR_EL12
 //CHECK:  mrs x0, TRFCR_EL2           // encoding: [0x20,0x12,0x3c,0xd5]
 //CHECK:  mrs x0, TRFCR_EL12          // encoding: [0x20,0x12,0x3d,0xd5]
 
+//CHECK:  tsb csync                   // encoding: [0x5f,0x22,0x03,0xd5]
+
 //CHECK-ERROR: error: expected writable system register or pstate
 //CHECK-ERROR: msr TRFCR_EL1, x0
 //CHECK-ERROR:     ^
@@ -40,3 +44,5 @@ mrs x0, TRFCR_EL12
 //CHECK-ERROR: error: expected readable system register
 //CHECK-ERROR: mrs x0, TRFCR_EL12
 //CHECK-ERROR:         ^
+
+//CHECK-ERROR: error: instruction requires: armv8.4a
diff --git a/llvm/test/MC/ARM/armv8.4a-trace-error.s b/llvm/test/MC/ARM/armv8.4a-trace-error.s
new file mode 100644
index 00000000000..7ec80408f0e
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.4a-trace-error.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple arm -mattr=+v8.4a -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple thumb -mattr=+v8.4a -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+tsb
+tsb 0
+tsb #0
+tsb foo
+
+//CHECK-ERROR: error: too few operands for instruction
+//CHECK-ERROR: tsb
+//CHECK-ERROR: ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR: tsb 0
+//CHECK-ERROR:     ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR: tsb #0
+//CHECK-ERROR:     ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR: tsb foo
+//CHECK-ERROR:     ^
diff --git a/llvm/test/MC/ARM/armv8.4a-trace.s b/llvm/test/MC/ARM/armv8.4a-trace.s
new file mode 100644
index 00000000000..254f776f39f
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.4a-trace.s
@@ -0,0 +1,12 @@
+// RUN: llvm-mc -triple arm -mattr=+v8.4a -show-encoding < %s | FileCheck %s  --check-prefix=CHECK-A32
+// RUN: llvm-mc -triple thumb -mattr=+v8.4a -show-encoding < %s | FileCheck %s  --check-prefix=CHECK-T32
+// RUN: not llvm-mc -triple arm -mattr=-v8.4a -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+tsb csync
+
+//CHECK-A32: tsb csync                   @ encoding: [0x12,0xf0,0x20,0xe3]
+//CHECK-T32: tsb csync                   @ encoding: [0xaf,0xf3,0x12,0x80]
+
+//CHECK-NO-V84: error: invalid instruction
+//CHECK-NO-V84: tsb csync
+//CHECK-NO-V84: ^
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt
index d51157e08f9..feb9e8c6747 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt
@@ -7,6 +7,7 @@
 [0x20,0x12,0x38,0xd5]
 [0x20,0x12,0x3c,0xd5]
 [0x20,0x12,0x3d,0xd5]
+[0x5f,0x22,0x03,0xd5]
 
 #CHECK:  msr TRFCR_EL1, x0
 #CHECK:  msr TRFCR_EL2, x0
@@ -14,6 +15,7 @@
 #CHECK:  mrs x0, TRFCR_EL1
 #CHECK:  mrs x0, TRFCR_EL2
 #CHECK:  mrs x0, TRFCR_EL12
+#CHECK:  tsb csync
 
 #CHECK-NO-V84:  msr S3_0_C1_C2_1, x0
 #CHECK-NO-V84:  msr S3_4_C1_C2_1, x0
@@ -21,3 +23,4 @@
 #CHECK-NO-V84:  mrs x0, S3_0_C1_C2_1
 #CHECK-NO-V84:  mrs x0, S3_4_C1_C2_1
 #CHECK-NO-V84:  mrs x0, S3_5_C1_C2_1
+#CHECK-NO-V84:  hint #18
diff --git a/llvm/test/MC/Disassembler/ARM/armv8.4a-trace-a32.txt b/llvm/test/MC/Disassembler/ARM/armv8.4a-trace-a32.txt
new file mode 100644
index 00000000000..d53cf5e49d9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/armv8.4a-trace-a32.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x12,0xf0,0x20,0xe3]
+
+#CHECK: tsb csync
+
+#CHECK-NO-V84: warning: invalid instruction encoding
+#CHECK-NO-V84: [0x12,0xf0,0x20,0xe3]
+#CHECK-NO-V84:  ^
diff --git a/llvm/test/MC/Disassembler/ARM/armv8.4a-trace-t32.txt b/llvm/test/MC/Disassembler/ARM/armv8.4a-trace-t32.txt
new file mode 100644
index 00000000000..5b062cc6ef4
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/armv8.4a-trace-t32.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0xaf,0xf3,0x12,0x80]
+
+#CHECK: tsb csync
+
+#CHECK-NO-V84: warning: invalid instruction encoding
+#CHECK-NO-V84: [0xaf,0xf3,0x12,0x80]
+#CHECK-NO-V84:  ^