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authorNicolai Haehnle <nhaehnle@gmail.com>2016-04-12 16:10:38 +0000
committerNicolai Haehnle <nhaehnle@gmail.com>2016-04-12 16:10:38 +0000
commit279970c0dc769dc24e5b66ed8fa6fcdc7653d4f4 (patch)
tree75fe7a80883d4d7bcbf3508519b27a53fe667829 /llvm/test
parent2f70584ae62056811007da1c1c89678c2c72c673 (diff)
downloadbcm5719-llvm-279970c0dc769dc24e5b66ed8fa6fcdc7653d4f4.tar.gz
bcm5719-llvm-279970c0dc769dc24e5b66ed8fa6fcdc7653d4f4.zip
AMDGPU/SI: Fix a mis-compilation of multi-level breaks
Summary: Under certain circumstances, multi-level breaks (or what is understood by the control flow passes as such) could be miscompiled in a way that causes infinite loops, by emitting incorrect control flow intrinsics. This fixes a hang in dEQP-GLES3.functional.shaders.loops.while_dynamic_iterations.conditional_continue_vertex Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18967 llvm-svn: 266088
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AMDGPU/multilevel-break.ll41
1 files changed, 41 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
new file mode 100644
index 00000000000..e1130c9125e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
@@ -0,0 +1,41 @@
+; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck %s
+
+; CHECK-LABEL: {{^}}define amdgpu_vs void @main
+; CHECK: main_body:
+; CHECK: LOOP.outer:
+; CHECK: LOOP:
+; CHECK: [[if:%[0-9]+]] = call { i1, i64 } @llvm.amdgcn.if(
+; CHECK: [[if_exec:%[0-9]+]] = extractvalue { i1, i64 } [[if]], 1
+;
+; CHECK: Flow:
+;
+; Ensure two else.break calls, for both the inner and outer loops
+;
+; CHECK: call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
+; CHECK-NEXT: call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
+; CHECK-NEXT: call void @llvm.amdgcn.end.cf
+;
+; CHECK: Flow1:
+define amdgpu_vs void @main(<4 x float> %vec, i32 %ub, i32 %cont) {
+main_body:
+ br label %LOOP.outer
+
+LOOP.outer: ; preds = %ENDIF, %main_body
+ %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
+ br label %LOOP
+
+LOOP: ; preds = %ENDIF, %LOOP.outer
+ %tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
+ %tmp47 = add i32 %tmp45, 1
+ %tmp48 = icmp slt i32 %tmp45, %ub
+ br i1 %tmp48, label %ENDIF, label %IF
+
+IF: ; preds = %LOOP
+ ret void
+
+ENDIF: ; preds = %LOOP
+ %tmp51 = icmp eq i32 %tmp47, %cont
+ br i1 %tmp51, label %LOOP, label %LOOP.outer
+}
+
+attributes #0 = { nounwind readnone }
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