GlobalISel: remove G_TYPE and G_PHI

These instructions were only necessary when type information was stored in the
MachineInstr (because only generic MachineInstrs possessed a type). Now that
it's in MachineRegisterInfo, COPY and PHI work fine.

llvm-svn: 281037

10 files changed, 17 insertions, 17 deletions

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 0a660e39b90..e462400b3cf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -325,7 +325,7 @@ define void @intrinsics(i32 %cur, i32 %bits) {
 ; CHECK: [[FALSE]]:
 ; CHECK:     [[RES2:%[0-9]+]](s32) = G_LOAD
 
-; CHECK:     [[RES:%[0-9]+]](s32) = G_PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
+; CHECK:     [[RES:%[0-9]+]](s32) = PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
 ; CHECK:     %w0 = COPY [[RES]]
 define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
   br i1 %tst, label %true, label %false
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 0dae823631e..0c4ce1ab355 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_and_small
     ; CHECK: %4(s8) = G_AND %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_AND %2, %3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index ba87b97b7ad..3037cd4271b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -34,7 +34,7 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    %0(s64) = G_TYPE %x0
+    %0(s64) = COPY %x0
 
     ; CHECK: %1(s1) = G_TRUNC %0
     ; CHECK: %2(s8) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
index 498d9039c02..7218ff8625c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
@@ -21,8 +21,8 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x0
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x0
 
     %2(s32) = G_TRUNC %0
     %3(s32) = G_TRUNC %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
index 308f8cc5634..55a12e14740 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
@@ -15,10 +15,10 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_copy
-    ; CHECK: %0(s64) = G_TYPE %x0
+    ; CHECK: %0(s64) = COPY %x0
     ; CHECK-NEXT: %x0 = COPY %0
 
-    %0(s64) = G_TYPE %x0
+    %0(s64) = COPY %x0
     %x0 = COPY %0
 ...
 
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index 25a34ebedd7..b4a054907d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_mul_small
     ; CHECK: %4(s8) = G_MUL %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_MUL %2, %3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index b85f195ddb1..a15ad4cf950 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_or_small
     ; CHECK: %4(s8) = G_OR %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_OR %2, %3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 168c6183c20..f626033391a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_xor_small
     ; CHECK: %4(s8) = G_XOR %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_XOR %2, %3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir b/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
index 69b83474137..9a2f7f7e54f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
@@ -9,7 +9,7 @@
 ...
 ---
 # CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
-# CHECK: instruction: %vreg0<def>(s64) = G_TYPE
+# CHECK: instruction: %vreg0<def>(s64) = COPY
 # CHECK: operand 0: %vreg0<def>
 name:            test
 regBankSelected: true
@@ -18,5 +18,5 @@ registers:
 body: |
   bb.0:
    liveins: %x0
-   %0(s64) = G_TYPE %x0
+   %0(s64) = COPY %x0
 ...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir b/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
index 54fd078a39c..2149903d08a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
@@ -19,7 +19,7 @@ registers:
 body: |
   bb.0:
    liveins: %x0
-   %0 = G_TYPE %x0
+   %0 = COPY %x0
 
    ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
    ; CHECK: instruction: %vreg1<def> = G_ADD