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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-07-15 00:02:32 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-07-15 00:02:32 +0000 |
| commit | 2152a6c78b762e5bfcef4032067aa127b7ea385f (patch) | |
| tree | 7c4a5b8b03930ea4cf260dfbc21382053c3aa16d /llvm/test | |
| parent | 457f73eaeedd73b88f8eef0d3bcdca4185925b0b (diff) | |
| download | bcm5719-llvm-2152a6c78b762e5bfcef4032067aa127b7ea385f.tar.gz bcm5719-llvm-2152a6c78b762e5bfcef4032067aa127b7ea385f.zip | |
[DAGCombiner] Avoid calling method 'isShuffleMaskLegal' on illegal vector types.
This patch fixes a crasher in method 'DAGCombiner::visitOR' due to an invalid
call to method 'isShuffleMaskLegal'. On x86, method 'isShuffleMaskLegal'
always expects a legal vector value type in input.
With this patch, we immediately check if the input OR dag node has a legal
vector type; we only try to fold a OR dag node into a single shufflevector
if we know that the resulting shuffle will have a legal type.
This is to avoid calling method 'isShuffleMaskLegal' on a potentially
illegal vector value type.
Added a new test-case to file 'CodeGen/X86/combine-or.ll' to verify that
DAGCombiner doesn't crash in the attempt to check/combine an OR between shuffles
with illegal types.
llvm-svn: 213020
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-or.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll index ff807b98717..df3b9015add 100644 --- a/llvm/test/CodeGen/X86/combine-or.ll +++ b/llvm/test/CodeGen/X86/combine-or.ll @@ -266,4 +266,16 @@ define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: pslldq ; CHECK-NEXT: ret +; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle +; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to +; handle legal vector value types. +define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) { + %shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3> + %shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4> + %or = or <4 x i8> %shuf1, %shuf2 + ret <4 x i8> %or +} +; CHECK-LABEL: test_crash +; CHECK: movsd +; CHECK: ret |
