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| author | Dan Gohman <dan433584@gmail.com> | 2015-12-09 16:23:59 +0000 |
|---|---|---|
| committer | Dan Gohman <dan433584@gmail.com> | 2015-12-09 16:23:59 +0000 |
| commit | 1cf96c0c34a4398c2bc0531c649d56ca805d2e30 (patch) | |
| tree | cb1e96ce41ca58ef508322cef588816521136b99 /llvm/test | |
| parent | 07410ed234702081a1fa42f1bc950421147c2c6c (diff) | |
| download | bcm5719-llvm-1cf96c0c34a4398c2bc0531c649d56ca805d2e30.tar.gz bcm5719-llvm-1cf96c0c34a4398c2bc0531c649d56ca805d2e30.zip | |
[WebAssembly] Reintroduce ARGUMENT moving logic
Reinteroduce the code for moving ARGUMENTS back to the top of the basic block.
While the ARGUMENTS physical register prevents sinking and scheduling from
moving them, it does not appear to be sufficient to prevent SelectionDAG from
moving them down in the initial schedule. This patch introduces a patch that
moves them back to the top immediately after SelectionDAG runs.
This is still hopefully a temporary solution. http://reviews.llvm.org/D14750 is
one alternative, though the review has not been favorable, and proposed
alternatives are longer-term and have other downsides.
This fixes the main outstanding -verify-machineinstrs failures, so it adds
-verify-machineinstrs to several tests.
Differential Revision: http://reviews.llvm.org/D15377
llvm-svn: 255125
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/dead-vreg.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/phi.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/reg-stackify.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/switch.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/unreachable.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/varargs.ll | 2 |
6 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/dead-vreg.ll b/llvm/test/CodeGen/WebAssembly/dead-vreg.ll index cf1415c1982..b03e1569fde 100644 --- a/llvm/test/CodeGen/WebAssembly/dead-vreg.ll +++ b/llvm/test/CodeGen/WebAssembly/dead-vreg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false | FileCheck %s +; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s ; Check that unused vregs aren't assigned registers. diff --git a/llvm/test/CodeGen/WebAssembly/phi.ll b/llvm/test/CodeGen/WebAssembly/phi.ll index abbc1c59af3..bae8a7c9e3b 100644 --- a/llvm/test/CodeGen/WebAssembly/phi.ll +++ b/llvm/test/CodeGen/WebAssembly/phi.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false | FileCheck %s +; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s ; Test that phis are lowered. diff --git a/llvm/test/CodeGen/WebAssembly/reg-stackify.ll b/llvm/test/CodeGen/WebAssembly/reg-stackify.ll index af4a3501531..3c343434836 100644 --- a/llvm/test/CodeGen/WebAssembly/reg-stackify.ll +++ b/llvm/test/CodeGen/WebAssembly/reg-stackify.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false | FileCheck %s +; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s ; Test the register stackifier pass. diff --git a/llvm/test/CodeGen/WebAssembly/switch.ll b/llvm/test/CodeGen/WebAssembly/switch.ll index b146a239b41..7f6f6efff7d 100644 --- a/llvm/test/CodeGen/WebAssembly/switch.ll +++ b/llvm/test/CodeGen/WebAssembly/switch.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false -disable-block-placement | FileCheck %s +; RUN: llc < %s -asm-verbose=false -disable-block-placement -verify-machineinstrs | FileCheck %s ; Test switch instructions. Block placement is disabled because it reorders ; the blocks in a way that isn't interesting here. diff --git a/llvm/test/CodeGen/WebAssembly/unreachable.ll b/llvm/test/CodeGen/WebAssembly/unreachable.ll index e14c58876ed..414767e5c35 100644 --- a/llvm/test/CodeGen/WebAssembly/unreachable.ll +++ b/llvm/test/CodeGen/WebAssembly/unreachable.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -asm-verbose=false | FileCheck %s -; RUN: llc < %s -asm-verbose=false -fast-isel | FileCheck %s +; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -asm-verbose=false -fast-isel -verify-machineinstrs | FileCheck %s ; Test that LLVM unreachable instruction and trap intrinsic are lowered to ; wasm unreachable diff --git a/llvm/test/CodeGen/WebAssembly/varargs.ll b/llvm/test/CodeGen/WebAssembly/varargs.ll index bda0dd779e6..10846f2a989 100644 --- a/llvm/test/CodeGen/WebAssembly/varargs.ll +++ b/llvm/test/CodeGen/WebAssembly/varargs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false | FileCheck %s +; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s ; Test varargs constructs. |
