[TableGen] AsmMatcher: Add AsmVariantName to Instruction class.

Summary:
This allows specifying instructions that are available only in specific assembler variant. If AsmVariantName is specified then instruction will be presented only in MatchTable for this variant. If not specified then assembler variants will be determined based on AsmString.
Also this allows splitting assembler match tables in same way as it is done in dissasembler.

Reviewers: ab, tstellarAMD, craig.topper, vpykhtin

Subscribers: wdng

Differential Revision: https://reviews.llvm.org/D24249

llvm-svn: 280952

1 files changed, 46 insertions, 0 deletions

diff --git a/llvm/test/TableGen/AsmVariant.td b/llvm/test/TableGen/AsmVariant.td
new file mode 100644
index 00000000000..6c50241e5ae
--- /dev/null
+++ b/llvm/test/TableGen/AsmVariant.td
@@ -0,0 +1,46 @@
+// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
+
+// Check that cpecifying AsmVariant works correctly
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+
+def FooAsmParserVariant : AsmParserVariant {
+  let Variant = 0;
+  let Name = "Foo";
+}
+
+def BarAsmParserVariant : AsmParserVariant {
+  let Variant = 1;
+  let Name = "Bar";
+}
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+  let AssemblyParserVariants = [FooAsmParserVariant, BarAsmParserVariant];
+}
+
+def Reg : Register<"reg">;
+
+def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def foo : Instruction {
+  let Size = 2;
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  let AsmString = "foo";
+  let AsmVariantName = "Foo";
+}
+
+def BarAlias : InstAlias<"bar", (foo)> {
+  string AsmVariantName = "Bar";
+}
+
+// CHECK: static const MatchEntry MatchTable0[] = {
+// CHECK-NEXT: /* foo */, Arch::foo
+// CHECK-NEXT: };
+
+// CHECK: static const MatchEntry MatchTable1[] = {
+// CHECK-NEXT: /* bar */, Arch::foo
+// CHECK-NEXT: };