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| author | Matthias Braun <matze@braunis.de> | 2016-09-23 18:28:31 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-09-23 18:28:31 +0000 |
| commit | 1acb55e67c554fabc768d52b4dcab32e474f83cb (patch) | |
| tree | 631dbd288e629c43880994eee26a7601f84d22bf /llvm/test | |
| parent | 6e8607527c1213dbf108d58831e7ce8fc8dc3e1b (diff) | |
| download | bcm5719-llvm-1acb55e67c554fabc768d52b4dcab32e474f83cb.tar.gz bcm5719-llvm-1acb55e67c554fabc768d52b4dcab32e474f83cb.zip | |
ScheduleDAG: Match enum names when printing sdep kinds
It is less confusing to have the same names in the debug print as the
enum members.
llvm-svn: 282273
Diffstat (limited to 'llvm/test')
5 files changed, 22 insertions, 22 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll index 0b8f7a19b48..4930c493d62 100644 --- a/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll +++ b/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -13,9 +13,9 @@ ; CHECK: SU(2): STRWui %WZR ; CHECK: SU(3): %X21<def>, %X20<def> = LDPXi %SP ; CHECK: Predecessors: -; CHECK-NEXT: out SU(0) -; CHECK-NEXT: out SU(0) -; CHECK-NEXT: ch SU(0) +; CHECK-NEXT: out SU(0) +; CHECK-NEXT: out SU(0) +; CHECK-NEXT: ord SU(0) ; CHECK-NEXT: Successors: define void @test1() { entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll index 07373ccedc5..0ee74d1f782 100644 --- a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll +++ b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll @@ -8,8 +8,8 @@ ; CHECK: shiftable ; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0 ; CHECK: Successors: -; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2 -; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2 +; CHECK-NEXT: data SU(4): Latency=1 Reg=%vreg2 +; CHECK-NEXT: data SU(3): Latency=2 Reg=%vreg2 ; CHECK: ********** INTERVALS ********** define i64 @shiftable(i64 %A, i64 %B) { %tmp0 = sub i64 %B, 20 diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll index 292fbb744ce..0ec754f97ec 100644 --- a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -7,11 +7,11 @@ ; CHECK: misched_bug:BB#0 entry ; CHECK: SU(2): %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0 ; CHECK: Successors: -; CHECK-NEXT: val SU(5): Latency=4 Reg=%vreg2 -; CHECK-NEXT: ch SU(4): Latency=0 +; CHECK-NEXT: data SU(5): Latency=4 Reg=%vreg2 +; CHECK-NEXT: ord SU(4): Latency=0 ; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 ; CHECK: Successors: -; CHECK: ch SU(4): Latency=0 +; CHECK: ord SU(4): Latency=0 ; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 ; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2 ; CHECK: ** ScheduleDAGMI::schedule picking next node diff --git a/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll b/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll index 59a3be905f1..0e4eb2b5fad 100644 --- a/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll +++ b/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll @@ -37,8 +37,8 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*, ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2> ; CHECK-NOT: SU ; CHECK: Successors: -; CHECK: ch SU([[DEPSTOREB:.*]]): Latency=0 -; CHECK: ch SU([[DEPSTOREA:.*]]): Latency=0 +; CHECK: ord SU([[DEPSTOREB:.*]]): Latency=0 +; CHECK: ord SU([[DEPSTOREA:.*]]): Latency=0 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4> ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3> diff --git a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index 6f92613fa1f..9dcfe5007c0 100644 --- a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -6,23 +6,23 @@ ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}}Volatile -; CHECK-NOT: ch SU -; CHECK: ch SU(3): Latency=1 -; CHECK-NOT: ch SU +; CHECK-NOT: ord SU +; CHECK: ord SU(3): Latency=1 +; CHECK-NOT: ord SU ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile -; CHECK-NOT: ch SU -; CHECK: ch SU(2): Latency=1 -; CHECK-NOT: ch SU +; CHECK-NOT: ord SU +; CHECK: ord SU(2): Latency=1 +; CHECK-NOT: ord SU ; CHECK: Successors: ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}} -; CHECK-NOT: ch SU -; CHECK: ch SU(3): Latency=1 -; CHECK-NOT: ch SU +; CHECK-NOT: ord SU +; CHECK: ord SU(3): Latency=1 +; CHECK-NOT: ord SU ; CHECK: SU(3){{.*}}LDR{{.*}} -; CHECK-NOT: ch SU -; CHECK: ch SU(2): Latency=1 -; CHECK-NOT: ch SU +; CHECK-NOT: ord SU +; CHECK: ord SU(2): Latency=1 +; CHECK-NOT: ord SU ; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: |
