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| author | Tim Northover <tnorthover@apple.com> | 2014-04-01 13:22:02 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-01 13:22:02 +0000 |
| commit | 1351030801098e15e6781c67132ea23e55aed77a (patch) | |
| tree | 3f89b8f57f2eff6429827d7cd5c0e4d5f2b0e5f9 /llvm/test | |
| parent | 56b6ee9833137e0e79667f8e4378895fed5dc2c2 (diff) | |
| download | bcm5719-llvm-1351030801098e15e6781c67132ea23e55aed77a.tar.gz bcm5719-llvm-1351030801098e15e6781c67132ea23e55aed77a.zip | |
ARM: add cyclone CPU with ZeroCycleZeroing feature.
The Cyclone CPU is similar to swift for most LLVM purposes, but does have two
preferred instructions for zeroing a VFP register. This teaches LLVM about
them.
llvm-svn: 205309
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/zero-cycle-zero.ll | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/zero-cycle-zero.ll b/llvm/test/CodeGen/ARM/zero-cycle-zero.ll new file mode 100644 index 00000000000..121a87f5b84 --- /dev/null +++ b/llvm/test/CodeGen/ARM/zero-cycle-zero.ll @@ -0,0 +1,70 @@ +; RUN: llc -mtriple=armv8 -mcpu=cyclone < %s | FileCheck %s --check-prefix=CHECK-CYCLONE +; RUN: llc -mtriple=armv8 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK-SWIFT + +declare arm_aapcs_vfpcc void @take_vec64(<2 x i32>) + +define void @test_vec64() { +; CHECK-CYCLONE-LABEL: test_vec64: +; CHECK-SWIFT-LABEL: test_vec64: + + call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>) + call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>) +; CHECK-CYCLONE-NOT: vmov.f64 d0, +; CHECK-CYCLONE: vmov.i32 d0, #0 +; CHECK-CYCLONE: bl +; CHECK-CYCLONE: vmov.i32 d0, #0 +; CHECK-CYCLONE: bl + +; CHECK-SWIFT: vmov.f64 [[ZEROREG:d[0-9]+]], +; CHECK-SWIFT: vmov.i32 [[ZEROREG]], #0 +; CHECK-SWIFT: vorr d0, [[ZEROREG]], [[ZEROREG]] +; CHECK-SWIFT: bl +; CHECK-SWIFT: vorr d0, [[ZEROREG]], [[ZEROREG]] +; CHECK-SWIFT: bl + + ret void +} + +declare arm_aapcs_vfpcc void @take_vec128(<8 x i16>) + +define void @test_vec128() { +; CHECK-CYCLONE-LABEL: test_vec128: +; CHECK-SWIFT-LABEL: test_vec128: + + call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>) + call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>) +; CHECK-CYCLONE-NOT: vmov.f64 [[ZEROREG:d[0-9]+]], +; CHECK-CYCLONE: vmov.i32 q0, #0 +; CHECK-CYCLONE: bl +; CHECK-CYCLONE: vmov.i32 q0, #0 +; CHECK-CYCLONE: bl + +; CHECK-SWIFT-NOT: vmov.f64 [[ZEROREG:d[0-9]+]], +; CHECK-SWIFT: vmov.i32 [[ZEROREG:q[0-9]+]], #0 +; CHECK-SWIFT: vorr q0, [[ZEROREG]], [[ZEROREG]] +; CHECK-SWIFT: bl +; CHECK-SWIFT: vorr q0, [[ZEROREG]], [[ZEROREG]] +; CHECK-SWIFT: bl + + ret void +} + +declare void @take_i32(i32) + +define void @test_i32() { +; CHECK-CYCLONE-LABEL: test_i32: +; CHECK-SWIFT-LABEL: test_i32: + + call arm_aapcs_vfpcc void @take_i32(i32 0) + call arm_aapcs_vfpcc void @take_i32(i32 0) +; CHECK-CYCLONE-NOT: vmov.f64 [[ZEROREG:d[0-9]+]], +; CHECK-CYCLONE: mov r0, #0 +; CHECK-CYCLONE: bl +; CHECK-CYCLONE: mov r0, #0 +; CHECK-CYCLONE: bl + +; It doesn't particularly matter what Swift does here, there isn't carefully +; crafted behaviour that we might break in Cyclone. + + ret void +} |
