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| author | Vladimir Sukharev <vladimir.sukharev@arm.com> | 2015-04-16 11:34:25 +0000 |
|---|---|---|
| committer | Vladimir Sukharev <vladimir.sukharev@arm.com> | 2015-04-16 11:34:25 +0000 |
| commit | 0e0f8d2c1ff19d2a13ea65d31db178025beaa51b (patch) | |
| tree | 5985c583e4cb925c9c2b206507a832c58a4d3efc /llvm/test | |
| parent | 1021040de33fe5fb508e695f9c16a0707374a016 (diff) | |
| download | bcm5719-llvm-0e0f8d2c1ff19d2a13ea65d31db178025beaa51b.tar.gz bcm5719-llvm-0e0f8d2c1ff19d2a13ea65d31db178025beaa51b.zip | |
[ARM] Add v8.1a "Privileged Access Never" extension
Reviewers: jmolloy
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8504
llvm-svn: 235087
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s | 32 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/armv8.1a.txt | 16 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt | 12 |
3 files changed, 60 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s b/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s index 3101d19284e..005f27bb398 100644 --- a/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s +++ b/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s @@ -172,3 +172,35 @@ //CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0] //CHECK-V8: ^ + + setpan #0 +//CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6] +//CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1] +//CHECK-V8: error: instruction requires: armv8.1a +//CHECK-V8: setpan #0 +//CHECK-V8: ^ + + setpan #1 +//CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6] +//CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1] +//CHECK-V8: error: instruction requires: armv8.1a +//CHECK-V8: setpan #1 +//CHECK-V8: ^ + setpan + setpan #-1 + setpan #2 +//CHECK-ERROR: error: too few operands for instruction +//CHECK-ERROR: setpan +//CHECK-ERROR: ^ +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR: setpan #-1 +//CHECK-ERROR: ^ +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR: setpan #2 +//CHECK-ERROR: ^ + + it eq + setpaneq #0 +//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified +//CHECK-THUMB-ERROR: setpaneq #0 +//CHECK-THUMB-ERROR: ^ diff --git a/llvm/test/MC/Disassembler/ARM/armv8.1a.txt b/llvm/test/MC/Disassembler/ARM/armv8.1a.txt index de0c89ee790..929643bd561 100644 --- a/llvm/test/MC/Disassembler/ARM/armv8.1a.txt +++ b/llvm/test/MC/Disassembler/ARM/armv8.1a.txt @@ -34,3 +34,19 @@ # CHECK-V8: [0x42,0x0f,0x92,0xf3] # CHECK-V8: warning: invalid instruction encoding # CHECK-V8: [0x42,0x0f,0xa1,0xf2] + +# The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN +# uses the encoding for the invalid NV predicate operand. This test checks that +# the disassembler is correctly disambiguating and decoding these instructions. + +[0x00 0x00 0x10 0xf1] +# CHECK: setpan #0 + +[0x00 0x02 0x10 0xf1] +# CHECK: setpan #1 + +[0x00 0x00 0x10 0xe1] +# CHECK: tst r0, r0 + +[0x00 0x02 0x10 0xe1] +# CHECK: tst r0, r0, lsl #4 diff --git a/llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt b/llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt index 10fea46694e..3de8c272ffa 100644 --- a/llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt +++ b/llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt @@ -96,3 +96,15 @@ # CHECK-V8: warning: invalid instruction encoding # CHECK-V8: [0xa2,0xff,0x42,0x0f] # CHECK-V8: ^ + +[0x10,0xb6] +# CHECK-V81a: setpan #0 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x10,0xb6] +# CHECK-V8: ^ + +[0x18,0xb6] +# CHECK-V81a: setpan #1 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x18,0xb6] +# CHECK-V8: ^ |
