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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-19 22:19:48 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-19 22:19:48 +0000 |
| commit | 066e9ec1e474ba04fcccbdf4055c73ef74c83dd4 (patch) | |
| tree | 657efa6641b06ab544d8cbff7016680380671988 /llvm/test | |
| parent | 58ce352d329835e6ceedb39b5d9ca30a9c143a35 (diff) | |
| download | bcm5719-llvm-066e9ec1e474ba04fcccbdf4055c73ef74c83dd4.tar.gz bcm5719-llvm-066e9ec1e474ba04fcccbdf4055c73ef74c83dd4.zip | |
Update tests.
llvm-svn: 138116
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/thumb2-mls.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/thumb2-mul.ll | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll index d0c4f3ae9d6..d148bbe41f2 100644 --- a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -6,9 +6,9 @@ define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { entry: ; CHECK: t: -; CHECK: muls r2, r3, r2 +; CHECK: muls r2, r2, r3 ; CHECK-NEXT: mul r0, r0, r1 -; CHECK-NEXT: muls r0, r2, r0 +; CHECK-NEXT: muls r0, r0, r2 %0 = mul nsw i32 %a, %b %1 = mul nsw i32 %c, %d %2 = mul nsw i32 %0, %1 diff --git a/llvm/test/CodeGen/Thumb2/thumb2-mls.ll b/llvm/test/CodeGen/Thumb2/thumb2-mls.ll index fc9e6bab48c..24c45c53fc8 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-mls.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-mls.ll @@ -15,5 +15,5 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) { ret i32 %tmp2 } ; CHECK: f2: -; CHECK: muls r0, r1 +; CHECK: muls r0, r0, r1 diff --git a/llvm/test/CodeGen/Thumb2/thumb2-mul.ll b/llvm/test/CodeGen/Thumb2/thumb2-mul.ll index 8d1de55b4dc..bb97d978cf2 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-mul.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-mul.ll @@ -2,7 +2,7 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) { ; CHECK: f1: -; CHECK: muls r0, r1 +; CHECK: muls r0, r0, r1 %tmp = mul i32 %a, %b ret i32 %tmp } |
