GlobalISel: simplify MachineIRBuilder interface.

MachineIRBuilder had weird before/after and beginning/end flags for the insert
point. Unfortunately the non-default means that instructions will be inserted
in reverse order which is almost never what anyone wants.

Really, I think we just want (like IRBuilder has) the ability to insert at any
C++ iterator-style point (i.e. before any instruction or before MBB.end()). So
this fixes MIRBuilders to behave like IRBuilders in this respect.

llvm-svn: 288980

5 files changed, 57 insertions, 22 deletions

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index ad353bfa9ab..a7c9b7233e4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -7,8 +7,9 @@ target triple = "aarch64--"
 
 ; Tests for add.
 ; CHECK-LABEL: name: addi64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
+; CHECK:      [[ARG1:%[0-9]+]](s64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0 
@@ -20,6 +21,7 @@ define i64 @addi64(i64 %arg1, i64 %arg2) {
 ; CHECK-LABEL: name: muli64
 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_MUL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
@@ -51,11 +53,13 @@ define void @allocai64() {
 ; CHECK-LABEL: name: uncondbr
 ; CHECK: body:
 ;
-; Entry basic block.
-; CHECK: {{[0-9a-zA-Z._-]+}}:
+; ABI/constant lowering basic block.
+; CHECK: {{bb.[0-9]+}}:
+; IR-level entry basic block
+; CHECK: {{bb.[0-9]+}}:
 ;
 ; Make sure we have one successor and only one.
-; CHECK-NEXT: successors: %[[END:[0-9a-zA-Z._-]+]](0x80000000)
+; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
 ;
 ; Check that we emit the correct branch.
 ; CHECK: G_BR %[[END]]
@@ -73,15 +77,18 @@ end:
 ; CHECK-LABEL: name: condbr
 ; CHECK: body:
 ;
-; Entry basic block.
-; CHECK: {{[0-9a-zA-Z._-]+}}:
+; ABI/constant lowering basic block.
+; CHECK: {{bb.[0-9]+}}:
+; CHECK: [[ADDR:%.*]](p0) = COPY %x0
+
+; IR-level entry basic block
+; CHECK: {{bb.[0-9]+}}:
 ;
 ; Make sure we have two successors
-; CHECK-NEXT: successors: %[[TRUE:[0-9a-zA-Z._-]+]](0x40000000),
-; CHECK:                  %[[FALSE:[0-9a-zA-Z._-]+]](0x40000000)
+; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
+; CHECK:                  %[[FALSE:bb.[0-9]+]](0x40000000)
 ;
 ; Check that we emit the correct branch.
-; CHECK: [[ADDR:%.*]](p0) = COPY %x0
 ; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0)
 ; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
 ; CHECK: G_BR %[[FALSE]]
@@ -104,6 +111,7 @@ false:
 ; CHECK-LABEL: name: ori64
 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_OR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
@@ -115,6 +123,7 @@ define i64 @ori64(i64 %arg1, i64 %arg2) {
 ; CHECK-LABEL: name: ori32
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_OR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -127,6 +136,7 @@ define i32 @ori32(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: xori64
 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_XOR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
@@ -138,6 +148,7 @@ define i64 @xori64(i64 %arg1, i64 %arg2) {
 ; CHECK-LABEL: name: xori32
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_XOR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -150,6 +161,7 @@ define i32 @xori32(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: andi64
 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_AND [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
@@ -161,6 +173,7 @@ define i64 @andi64(i64 %arg1, i64 %arg2) {
 ; CHECK-LABEL: name: andi32
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_AND [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -173,6 +186,7 @@ define i32 @andi32(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: subi64
 ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_SUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
@@ -184,6 +198,7 @@ define i64 @subi64(i64 %arg1, i64 %arg2) {
 ; CHECK-LABEL: name: subi32
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -383,8 +398,8 @@ next:
 }
 
 ; CHECK-LABEL: name: constant_int_start
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
 ; CHECK: [[TWO:%[0-9]+]](s32) = G_CONSTANT i32 2
+; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
 ; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[TWO]], [[ANSWER]]
 define i32 @constant_int_start() {
   %res = add i32 2, 42
@@ -436,6 +451,7 @@ define i64 @test_zext(i32 %in) {
 ; CHECK-LABEL: name: test_shl
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SHL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -448,6 +464,7 @@ define i32 @test_shl(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_lshr
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_LSHR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -459,6 +476,7 @@ define i32 @test_lshr(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_ashr
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_ASHR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -470,6 +488,7 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_sdiv
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -481,6 +500,7 @@ define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_udiv
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -492,6 +512,7 @@ define i32 @test_udiv(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_srem
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -503,6 +524,7 @@ define i32 @test_srem(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_urem
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
@@ -554,6 +576,7 @@ define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
 ; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0
 ; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1
 ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
+; CHECK: bb.1:
 ; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
 define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
@@ -565,6 +588,7 @@ define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
 ; CHECK-LABEL: name: test_fadd
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FADD [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
@@ -576,6 +600,7 @@ define float @test_fadd(float %arg1, float %arg2) {
 ; CHECK-LABEL: name: test_fsub
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FSUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
@@ -587,6 +612,7 @@ define float @test_fsub(float %arg1, float %arg2) {
 ; CHECK-LABEL: name: test_fmul
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FMUL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
@@ -598,6 +624,7 @@ define float @test_fmul(float %arg1, float %arg2) {
 ; CHECK-LABEL: name: test_fdiv
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
@@ -609,6 +636,7 @@ define float @test_fdiv(float %arg1, float %arg2) {
 ; CHECK-LABEL: name: test_frem
 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
+; CHECK: bb.1:
 ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
@@ -929,14 +957,18 @@ define void @test_large_const(i128* %addr) {
 
 ; When there was no formal argument handling (so the first BB was empty) we used
 ; to insert the constants at the end of the block, even if they were encountered
-; after the block's terminators had been emitted.
-define i32 @test_const_placement() {
+; after the block's terminators had been emitted. Also make sure the order is
+; correct.
+define i8* @test_const_placement() {
 ; CHECK-LABEL: name: test_const_placement
-; CHECK: [[VAL:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: G_BR
-
+; CHECK: bb.0:
+; CHECK:   [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
+; CHECK: bb.1:
+; CHECK:   G_BR
+; CHECK: bb.2:
+; CHECK:   [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
   br label %next
 
 next:
-  ret i32 42
+  ret i8* inttoptr(i32 42 to i8*)
 }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
index a340082d562..4e6b9cad4c3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
@@ -18,8 +18,8 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs)
 }
 
 ; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
 ; CHECK: [[C42:%[0-9]+]](s8) = G_CONSTANT i8 42
+; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
 ; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
 ; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index 5828d4246b1..4c6fff6ab28 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -162,9 +162,9 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
 }
 
 ; CHECK-LABEL: name: test_call_stack
-; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
-; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
 ; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
+; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
+; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
 ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
 ; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
 ; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index b1907aed4f0..c177390c040 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -9,14 +9,15 @@ declare i32 @llvm.eh.typeid.for(i8*)
 ; CHECK: name: bar
 ; CHECK: body:
 ; CHECK:   bb.0:
-; CHECK:     successors: %bb.2{{.*}}%bb.1
+; CHECK:   bb.1:
+; CHECK:     successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
 ; CHECK:     EH_LABEL
 ; CHECK:     %w0 = COPY
 ; CHECK:     BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
 ; CHECK:     {{%[0-9]+}}(s32) = COPY %w0
 ; CHECK:     EH_LABEL
 
-; CHECK:   bb.1
+; CHECK:   [[BAD]] (landing-pad):
 ; CHECK:     EH_LABEL
 ; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
 ; CHECK:     [[SEL:%[0-9]+]](p0) = COPY %x1
@@ -25,7 +26,7 @@ declare i32 @llvm.eh.typeid.for(i8*)
 ; CHECK:     %x0 = COPY [[PTR_RET]]
 ; CHECK:     %w1 = COPY [[SEL_RET]]
 
-; CHECK:   bb.2:
+; CHECK:   [[GOOD]]:
 ; CHECK:     [[SEL:%[0-9]+]](s32) = G_CONSTANT i32 1
 ; CHECK:     {{%[0-9]+}}(s128) = G_INSERT {{%[0-9]+}}(s128), [[SEL]](s32), 64
 
diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
index 0332d3e9208..e847eda4eeb 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
@@ -25,6 +25,8 @@ define void @test_void_return() {
 ; CHECK-NEXT:   hasMustTailInVarArgFunc: false
 ; CHECK-NEXT: body:
 ; CHECK-NEXT:   bb.0:
+; CHECK-NEXT:     successors: %bb.1(0x80000000)
+; CHECK:        bb.1:
 ; CHECK-NEXT:     RET 0
 entry:
   ret void