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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 22:44:19 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 22:44:19 +0000 |
| commit | 0599297cb42d6718e0c40f62189bfa6cf8bf9e7b (patch) | |
| tree | 89546f7188554f5ac65059a41a7dd89e9926ad2a /llvm/test | |
| parent | e6264cf66114b336a18b41dd8096a0b74943d90a (diff) | |
| download | bcm5719-llvm-0599297cb42d6718e0c40f62189bfa6cf8bf9e7b.tar.gz bcm5719-llvm-0599297cb42d6718e0c40f62189bfa6cf8bf9e7b.zip | |
R600/SI: Commute instructions to enable more folding opportunities
llvm-svn: 225410
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/R600/mulhu.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/sdiv.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/use-sgpr-multiple-times.ll | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/R600/mulhu.ll b/llvm/test/CodeGen/R600/mulhu.ll index 146c92f8905..86597171230 100644 --- a/llvm/test/CodeGen/R600/mulhu.ll +++ b/llvm/test/CodeGen/R600/mulhu.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0xaaaaaaab -;CHECK: v_mul_hi_u32 v0, {{[sv][0-9]+}}, {{v[0-9]+}} +;CHECK: v_mul_hi_u32 v0, {{v[0-9]+}}, {{s[0-9]+}} ;CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v0 define void @test(i32 %p) { diff --git a/llvm/test/CodeGen/R600/sdiv.ll b/llvm/test/CodeGen/R600/sdiv.ll index 8d4208cb585..c635c0569e8 100644 --- a/llvm/test/CodeGen/R600/sdiv.ll +++ b/llvm/test/CodeGen/R600/sdiv.ll @@ -35,7 +35,7 @@ define void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; FUNC-LABEL: {{^}}slow_sdiv_i32_3435: ; SI: buffer_load_dword [[VAL:v[0-9]+]], ; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b -; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[VAL]], [[MAGIC]] +; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[MAGIC]], [[VAL]] ; SI: v_add_i32 ; SI: v_lshrrev_b32 ; SI: v_ashrrev_i32 diff --git a/llvm/test/CodeGen/R600/use-sgpr-multiple-times.ll b/llvm/test/CodeGen/R600/use-sgpr-multiple-times.ll index 2c6ae1eae67..97d73ba74bc 100644 --- a/llvm/test/CodeGen/R600/use-sgpr-multiple-times.ll +++ b/llvm/test/CodeGen/R600/use-sgpr-multiple-times.ll @@ -41,7 +41,7 @@ define void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, floa ; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc ; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] -; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]] +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]] ; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 { %fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1 @@ -53,7 +53,7 @@ define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, floa ; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc ; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] -; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]] +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]] ; SI: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 { %fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1 |
