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| author | Jim Grosbach <grosbach@apple.com> | 2009-11-15 21:45:34 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2009-11-15 21:45:34 +0000 |
| commit | 01c1cae34d68de646f262a19440c61c6f3479b5b (patch) | |
| tree | c1cb265286862e1c8dbaf041e332cca45ccf7280 /llvm/test | |
| parent | 74ae3e5b0efdb637c061cded4e086ae48539734d (diff) | |
| download | bcm5719-llvm-01c1cae34d68de646f262a19440c61c6f3479b5b.tar.gz bcm5719-llvm-01c1cae34d68de646f262a19440c61c6f3479b5b.zip | |
Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/spill-q.ll | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/spill-q.ll b/llvm/test/CodeGen/ARM/spill-q.ll index f4b27a7603e..6b44210af74 100644 --- a/llvm/test/CodeGen/ARM/spill-q.ll +++ b/llvm/test/CodeGen/ARM/spill-q.ll @@ -11,8 +11,9 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly define arm_apcscc void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: -; CHECK: vstmia sp -; CHECK: vldmia sp +; CHECK: bic sp, sp, #15 +; CHECK: vst1.64 {{.*}}sp @128 +; CHECK: vld1.64 {{.*}}sp @128 entry: %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1] store float 6.300000e+01, float* undef, align 4 diff --git a/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll b/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll index 0a7221c6174..6c6a7e19af0 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll @@ -11,8 +11,9 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly define arm_apcscc void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: -; CHECK: vstmia sp -; CHECK: vldmia sp +; CHECK: bic sp, sp, #15 +; CHECK: vst1.64 {{.*}}sp @128 +; CHECK: vld1.64 {{.*}}sp @128 entry: %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1] store float 6.300000e+01, float* undef, align 4 |
