[llvm-mca][x86] Add PREFETCHW instruction resource tests

These aren't just available via 3DNow! so test for them separately as well.

llvm-svn: 338584

7 files changed, 268 insertions, 0 deletions

diff --git a/llvm/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s
new file mode 100644
index 00000000000..e20c30ab581
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -instruction-tables < %s | FileCheck %s
+
+prefetch    (%rax)
+prefetchw   (%rax)
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      5     0.50    *      *            prefetch	(%rax)
+# CHECK-NEXT:  1      5     0.50    *      *            prefetchw	(%rax)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - BWDivider
+# CHECK-NEXT: [1]   - BWFPDivider
+# CHECK-NEXT: [2]   - BWPort0
+# CHECK-NEXT: [3]   - BWPort1
+# CHECK-NEXT: [4]   - BWPort2
+# CHECK-NEXT: [5]   - BWPort3
+# CHECK-NEXT: [6]   - BWPort4
+# CHECK-NEXT: [7]   - BWPort5
+# CHECK-NEXT: [8]   - BWPort6
+# CHECK-NEXT: [9]   - BWPort7
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
+# CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
+# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -     prefetch	(%rax)
+# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -     prefetchw	(%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s
new file mode 100644
index 00000000000..2a94e77e52f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s
@@ -0,0 +1,42 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -instruction-tables < %s | FileCheck %s
+
+prefetch    (%rax)
+prefetchw   (%rax)
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      5     1.00    *      *            prefetch	(%rax)
+# CHECK-NEXT:  1      5     1.00    *      *            prefetchw	(%rax)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - JALU0
+# CHECK-NEXT: [1]   - JALU1
+# CHECK-NEXT: [2]   - JDiv
+# CHECK-NEXT: [3]   - JFPA
+# CHECK-NEXT: [4]   - JFPM
+# CHECK-NEXT: [5]   - JFPU0
+# CHECK-NEXT: [6]   - JFPU1
+# CHECK-NEXT: [7]   - JLAGU
+# CHECK-NEXT: [8]   - JMul
+# CHECK-NEXT: [9]   - JSAGU
+# CHECK-NEXT: [10]  - JSTC
+# CHECK-NEXT: [11]  - JVALU0
+# CHECK-NEXT: [12]  - JVALU1
+# CHECK-NEXT: [13]  - JVIMUL
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
+# CHECK-NEXT:  -      -      -      -      -      -      -     2.00    -      -      -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
+# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -      -      -      -      -      -     prefetch	(%rax)
+# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -      -      -      -      -      -     prefetchw	(%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s
new file mode 100644
index 00000000000..b44b28c3725
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
+
+prefetch    (%rax)
+prefetchw   (%rax)
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      5     0.50    *      *            prefetch	(%rax)
+# CHECK-NEXT:  1      5     0.50    *      *            prefetchw	(%rax)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SBDivider
+# CHECK-NEXT: [1]   - SBFPDivider
+# CHECK-NEXT: [2]   - SBPort0
+# CHECK-NEXT: [3]   - SBPort1
+# CHECK-NEXT: [4]   - SBPort4
+# CHECK-NEXT: [5]   - SBPort5
+# CHECK-NEXT: [6.0] - SBPort23
+# CHECK-NEXT: [6.1] - SBPort23
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   1.00
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
+# CHECK-NEXT:  -      -      -      -      -      -     0.50   0.50   prefetch	(%rax)
+# CHECK-NEXT:  -      -      -      -      -      -     0.50   0.50   prefetchw	(%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s
new file mode 100644
index 00000000000..ec0b887cdf2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=slm -instruction-tables < %s | FileCheck %s
+
+prefetch    (%rax)
+prefetchw   (%rax)
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00    *      *            prefetch	(%rax)
+# CHECK-NEXT:  1      3     1.00    *      *            prefetchw	(%rax)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SLMDivider
+# CHECK-NEXT: [1]   - SLMFPDivider
+# CHECK-NEXT: [2]   - SLMFPMultiplier
+# CHECK-NEXT: [3]   - SLM_FPC_RSV0
+# CHECK-NEXT: [4]   - SLM_FPC_RSV1
+# CHECK-NEXT: [5]   - SLM_IEC_RSV0
+# CHECK-NEXT: [6]   - SLM_IEC_RSV1
+# CHECK-NEXT: [7]   - SLM_MEC_RSV
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -      -      -      -      -      -     2.00
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -      -      -      -      -      -     1.00   prefetch	(%rax)
+# CHECK-NEXT:  -      -      -      -      -      -      -     1.00   prefetchw	(%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s
new file mode 100644
index 00000000000..38195c0b356
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -instruction-tables < %s | FileCheck %s
+
+prefetch    (%rax)
+prefetchw   (%rax)
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      5     0.50    *      *            prefetch	(%rax)
+# CHECK-NEXT:  1      5     0.50    *      *            prefetchw	(%rax)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SKLDivider
+# CHECK-NEXT: [1]   - SKLFPDivider
+# CHECK-NEXT: [2]   - SKLPort0
+# CHECK-NEXT: [3]   - SKLPort1
+# CHECK-NEXT: [4]   - SKLPort2
+# CHECK-NEXT: [5]   - SKLPort3
+# CHECK-NEXT: [6]   - SKLPort4
+# CHECK-NEXT: [7]   - SKLPort5
+# CHECK-NEXT: [8]   - SKLPort6
+# CHECK-NEXT: [9]   - SKLPort7
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
+# CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
+# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -     prefetch	(%rax)
+# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -     prefetchw	(%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s
new file mode 100644
index 00000000000..ccafef5b9e4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -instruction-tables < %s | FileCheck %s
+
+prefetch    (%rax)
+prefetchw   (%rax)
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      5     0.50    *      *            prefetch	(%rax)
+# CHECK-NEXT:  1      5     0.50    *      *            prefetchw	(%rax)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SKXDivider
+# CHECK-NEXT: [1]   - SKXFPDivider
+# CHECK-NEXT: [2]   - SKXPort0
+# CHECK-NEXT: [3]   - SKXPort1
+# CHECK-NEXT: [4]   - SKXPort2
+# CHECK-NEXT: [5]   - SKXPort3
+# CHECK-NEXT: [6]   - SKXPort4
+# CHECK-NEXT: [7]   - SKXPort5
+# CHECK-NEXT: [8]   - SKXPort6
+# CHECK-NEXT: [9]   - SKXPort7
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
+# CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
+# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -     prefetch	(%rax)
+# CHECK-NEXT:  -      -      -      -     0.50   0.50    -      -      -      -     prefetchw	(%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s
new file mode 100644
index 00000000000..47a52fb0638
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -instruction-tables < %s | FileCheck %s
+
+prefetch    (%rax)
+prefetchw   (%rax)
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      8     0.50    *      *            prefetch	(%rax)
+# CHECK-NEXT:  1      8     0.50    *      *            prefetchw	(%rax)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - ZnAGU0
+# CHECK-NEXT: [1]   - ZnAGU1
+# CHECK-NEXT: [2]   - ZnALU0
+# CHECK-NEXT: [3]   - ZnALU1
+# CHECK-NEXT: [4]   - ZnALU2
+# CHECK-NEXT: [5]   - ZnALU3
+# CHECK-NEXT: [6]   - ZnDivider
+# CHECK-NEXT: [7]   - ZnFPU0
+# CHECK-NEXT: [8]   - ZnFPU1
+# CHECK-NEXT: [9]   - ZnFPU2
+# CHECK-NEXT: [10]  - ZnFPU3
+# CHECK-NEXT: [11]  - ZnMultiplier
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]
+# CHECK-NEXT: 1.00   1.00    -      -      -      -      -      -      -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   Instructions:
+# CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     prefetch	(%rax)
+# CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     prefetchw	(%rax)