diff options
| author | Yaxun Liu <Yaxun.Liu@amd.com> | 2017-11-30 20:27:56 +0000 |
|---|---|---|
| committer | Yaxun Liu <Yaxun.Liu@amd.com> | 2017-11-30 20:27:56 +0000 |
| commit | 1db0f718b557971fa2a8ef04e6d54661e2c9cf84 (patch) | |
| tree | 7e70b27893bfd732626ab67a0360e9b061576688 /llvm/test/tools/llvm-objdump/AMDGPU | |
| parent | d4257565cfa4173492b0c4d0fa85d37b9fad6e2a (diff) | |
| download | bcm5719-llvm-1db0f718b557971fa2a8ef04e6d54661e2c9cf84.tar.gz bcm5719-llvm-1db0f718b557971fa2a8ef04e6d54661e2c9cf84.zip | |
[AMDGPU] Convert test/tools/llvm-objdump/AMDGPU/source-lines.ll to amdgiz
Differential Revision: https://reviews.llvm.org/D40653
llvm-svn: 319469
Diffstat (limited to 'llvm/test/tools/llvm-objdump/AMDGPU')
| -rw-r--r-- | llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll b/llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll index cc0c44e5315..7349f53fd89 100644 --- a/llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll +++ b/llvm/test/tools/llvm-objdump/AMDGPU/source-lines.ll @@ -1,7 +1,7 @@ ; RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %s > %t.ll -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj -O0 -o %t.o %t.ll -; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -disassemble -line-numbers %t.o | FileCheck --check-prefix=LINE %t.ll -; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -disassemble -source %t.o | FileCheck --check-prefix=SOURCE %t.ll +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -filetype=obj -O0 -o %t.o %t.ll +; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -disassemble -line-numbers %t.o | FileCheck --check-prefix=LINE %t.ll +; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -disassemble -source %t.o | FileCheck --check-prefix=SOURCE %t.ll ; Prologue. ; LINE: source_lines_test: @@ -37,29 +37,29 @@ ; ModuleID = 'source-lines.cl' source_filename = "source-lines.cl" -target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" -target triple = "amdgcn-amd-amdhsa" +target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5" +target triple = "amdgcn-amd-amdhsa-amdgiz" ; Function Attrs: noinline nounwind define amdgpu_kernel void @source_lines_test(i32 addrspace(1)* %Out) #0 !dbg !7 !kernel_arg_addr_space !12 !kernel_arg_access_qual !13 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !15 { entry: - %Out.addr = alloca i32 addrspace(1)*, align 4 - %var0 = alloca i32, align 4 - %var1 = alloca i32, align 4 - %var2 = alloca i32, align 4 - store i32 addrspace(1)* %Out, i32 addrspace(1)** %Out.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)** %Out.addr, metadata !16, metadata !17), !dbg !18 - call void @llvm.dbg.declare(metadata i32* %var0, metadata !19, metadata !17), !dbg !20 - store i32 1911, i32* %var0, align 4, !dbg !20 - call void @llvm.dbg.declare(metadata i32* %var1, metadata !21, metadata !17), !dbg !22 - store i32 2184, i32* %var1, align 4, !dbg !22 - call void @llvm.dbg.declare(metadata i32* %var2, metadata !23, metadata !17), !dbg !24 - %0 = load i32, i32* %var0, align 4, !dbg !25 - %1 = load i32, i32* %var1, align 4, !dbg !26 + %Out.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) + %var0 = alloca i32, align 4, addrspace(5) + %var1 = alloca i32, align 4, addrspace(5) + %var2 = alloca i32, align 4, addrspace(5) + store i32 addrspace(1)* %Out, i32 addrspace(1)* addrspace(5)* %Out.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %Out.addr, metadata !16, metadata !17), !dbg !18 + call void @llvm.dbg.declare(metadata i32 addrspace(5)* %var0, metadata !19, metadata !17), !dbg !20 + store i32 1911, i32 addrspace(5)* %var0, align 4, !dbg !20 + call void @llvm.dbg.declare(metadata i32 addrspace(5)* %var1, metadata !21, metadata !17), !dbg !22 + store i32 2184, i32 addrspace(5)* %var1, align 4, !dbg !22 + call void @llvm.dbg.declare(metadata i32 addrspace(5)* %var2, metadata !23, metadata !17), !dbg !24 + %0 = load i32, i32 addrspace(5)* %var0, align 4, !dbg !25 + %1 = load i32, i32 addrspace(5)* %var1, align 4, !dbg !26 %add = add nsw i32 %0, %1, !dbg !27 - store i32 %add, i32* %var2, align 4, !dbg !24 - %2 = load i32, i32* %var2, align 4, !dbg !28 - %3 = load i32 addrspace(1)*, i32 addrspace(1)** %Out.addr, align 4, !dbg !29 + store i32 %add, i32 addrspace(5)* %var2, align 4, !dbg !24 + %2 = load i32, i32 addrspace(5)* %var2, align 4, !dbg !28 + %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %Out.addr, align 4, !dbg !29 store i32 %2, i32 addrspace(1)* %3, align 4, !dbg !30 ret void, !dbg !31 } |
