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| author | Craig Topper <craig.topper@intel.com> | 2018-09-06 23:55:34 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-09-06 23:55:34 +0000 |
| commit | 37d68e4599677a57d0addf747ff3c30dfe39b14a (patch) | |
| tree | c2ec5997323d6db4912b668b66e54e8965b9263e /llvm/test/tools/llvm-objcopy/compress-debug-sections-zlib-gnu.test | |
| parent | 8c4db5da5fe4ec63c9968adfe4965c41ff16a8bf (diff) | |
| download | bcm5719-llvm-37d68e4599677a57d0addf747ff3c30dfe39b14a.tar.gz bcm5719-llvm-37d68e4599677a57d0addf747ff3c30dfe39b14a.zip | |
[X86] Add a test case showing failure to use the RMW form of ADC when the load is in operand 1 going into isel.
The ADC instruction is commutable, but we only have RMW isel patterns with a load on the left hand side. Nothing will canonicalize loads to the LHS on these ops. So we need two patterns.
llvm-svn: 341605
Diffstat (limited to 'llvm/test/tools/llvm-objcopy/compress-debug-sections-zlib-gnu.test')
0 files changed, 0 insertions, 0 deletions
