diff options
| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-24 16:19:08 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-24 16:19:08 +0000 |
| commit | 0626864fa472a0596c026d392a25110f77d13ed1 (patch) | |
| tree | 936321563327cf3c0c4660a12b9ce688a701126f /llvm/test/tools/llvm-mca/X86/intel-syntax.s | |
| parent | 9df3be3ccb175beb960d7c8456c89c8d94c4ff2d (diff) | |
| download | bcm5719-llvm-0626864fa472a0596c026d392a25110f77d13ed1.tar.gz bcm5719-llvm-0626864fa472a0596c026d392a25110f77d13ed1.zip | |
[llvm-mca] Default the output asm dialect used by the instruction printer to the input asm dialect.
The instruction printer used by llvm-mca to generate the performance report now
defaults the output assembly format to the format used for the input assembly
file.
On x86, the asm format can be either AT&T or Intel, depending on the
presence/absence of directive `.intel_syntax`.
Users can still specify a different assembly dialect with the command line flag
-output-asm-variant=<uint>.
llvm-svn: 330733
Diffstat (limited to 'llvm/test/tools/llvm-mca/X86/intel-syntax.s')
| -rw-r--r-- | llvm/test/tools/llvm-mca/X86/intel-syntax.s | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/llvm/test/tools/llvm-mca/X86/intel-syntax.s b/llvm/test/tools/llvm-mca/X86/intel-syntax.s new file mode 100644 index 00000000000..7513c422d0d --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/intel-syntax.s @@ -0,0 +1,37 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,INTEL +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=0 < %s | FileCheck %s -check-prefixes=ALL,ATT +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=1 < %s | FileCheck %s -check-prefixes=ALL,INTEL + + .intel_syntax noprefix + mov eax, 1 + mov ebx, 0ffh + imul esi, edi + lea eax, [rsi + rdi] + +# ALL: Iterations: 100 +# ALL-NEXT: Instructions: 400 +# ALL-NEXT: Total Cycles: 305 +# ALL-NEXT: Dispatch Width: 2 +# ALL-NEXT: IPC: 1.31 + +# ALL: Instruction Info: +# ALL-NEXT: [1]: #uOps +# ALL-NEXT: [2]: Latency +# ALL-NEXT: [3]: RThroughput +# ALL-NEXT: [4]: MayLoad +# ALL-NEXT: [5]: MayStore +# ALL-NEXT: [6]: HasSideEffects + +# INTEL: [1] [2] [3] [4] [5] [6] Instructions: +# INTEL-NEXT: 1 1 0.50 mov eax, 1 +# INTEL-NEXT: 1 1 0.50 mov ebx, 255 +# INTEL-NEXT: 2 3 1.00 imul esi, edi +# INTEL-NEXT: 1 1 0.50 lea eax, [rsi + rdi] + +# ATT: [1] [2] [3] [4] [5] [6] Instructions: +# ATT-NEXT: 1 1 0.50 movl $1, %eax +# ATT-NEXT: 1 1 0.50 movl $255, %ebx +# ATT-NEXT: 2 3 1.00 imull %edi, %esi +# ATT-NEXT: 1 1 0.50 leal (%rsi,%rdi), %eax + |
