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| author | Amara Emerson <aemerson@apple.com> | 2018-12-05 23:53:30 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2018-12-05 23:53:30 +0000 |
| commit | a0b15d8f3e61d7f47810c07fea56ecc88fccd2d0 (patch) | |
| tree | 80dd6f1ae63500ee055ac96fe69d0e7d01f0cd66 /llvm/test/Verifier | |
| parent | 8adc72d176bb51974b973ce17f50d510277cb1e5 (diff) | |
| download | bcm5719-llvm-a0b15d8f3e61d7f47810c07fea56ecc88fccd2d0.tar.gz bcm5719-llvm-a0b15d8f3e61d7f47810c07fea56ecc88fccd2d0.zip | |
[GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECTOR opcodes.
These opcodes are intended to subsume some of the capability of G_MERGE_VALUES,
as it was too powerful and thus complex to add deal with throughout the GISel
pipeline.
G_BUILD_VECTOR creates a vector value from a sequence of uniformly typed
scalar values. G_BUILD_VECTOR_TRUNC is a special opcode for handling scalar
operands which are larger than the destination vector element type, and
therefore does an implicit truncate.
G_CONCAT_VECTOR creates a vector by concatenating smaller, uniformly typed,
vectors together.
These will be used in a subsequent commit. This commit just adds the initial
infrastructure.
Differential Revision: https://reviews.llvm.org/D53594
llvm-svn: 348430
Diffstat (limited to 'llvm/test/Verifier')
| -rw-r--r-- | llvm/test/Verifier/gisel-g_build_vector.mir | 27 | ||||
| -rw-r--r-- | llvm/test/Verifier/gisel-g_build_vector_trunc.mir | 27 | ||||
| -rw-r--r-- | llvm/test/Verifier/gisel-g_concat_vector.mir | 29 |
3 files changed, 83 insertions, 0 deletions
diff --git a/llvm/test/Verifier/gisel-g_build_vector.mir b/llvm/test/Verifier/gisel-g_build_vector.mir new file mode 100644 index 00000000000..a40942ef47b --- /dev/null +++ b/llvm/test/Verifier/gisel-g_build_vector.mir @@ -0,0 +1,27 @@ +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# REQUIRES: global-isel, aarch64-registered-target +--- | + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-unknown-unknown" + + define i32 @g_build_vector() { + ret i32 0 + } + +... +--- +name: g_build_vector +legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _, preferred-register: '' } +liveins: +body: | + bb.0: + ; CHECK: Bad machine code: G_BUILD_VECTOR src operands total size don't match dest size + + %0(s32) = IMPLICIT_DEF + %1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0 +... diff --git a/llvm/test/Verifier/gisel-g_build_vector_trunc.mir b/llvm/test/Verifier/gisel-g_build_vector_trunc.mir new file mode 100644 index 00000000000..3b9b304b667 --- /dev/null +++ b/llvm/test/Verifier/gisel-g_build_vector_trunc.mir @@ -0,0 +1,27 @@ +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# REQUIRES: global-isel, aarch64-registered-target +--- | + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-unknown-unknown" + + define i32 @g_build_vector_trunc() { + ret i32 0 + } + +... +--- +name: g_build_vector_trunc +legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _, preferred-register: '' } +liveins: +body: | + bb.0: + ; CHECK: Bad machine code: G_BUILD_VECTOR_TRUNC source operand types are not larger than dest elt type + + %0(s32) = IMPLICIT_DEF + %1:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %0, %0 +... diff --git a/llvm/test/Verifier/gisel-g_concat_vector.mir b/llvm/test/Verifier/gisel-g_concat_vector.mir new file mode 100644 index 00000000000..640c4a4ceed --- /dev/null +++ b/llvm/test/Verifier/gisel-g_concat_vector.mir @@ -0,0 +1,29 @@ +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# REQUIRES: global-isel, aarch64-registered-target +--- | + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-unknown-unknown" + + define i32 @g_concat_vectors() { + ret i32 0 + } + +... +--- +name: g_concat_vectors +legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } +liveins: +body: | + bb.0: + ; CHECK: Bad machine code: G_CONCAT_VECTOR num dest and source elements should match + + %0(<2 x s32>) = IMPLICIT_DEF + %1(<2 x s32>) = IMPLICIT_DEF + %2:_(<2 x s32>) = G_CONCAT_VECTORS %0, %1 +... |

