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authorDan Gohman <gohman@apple.com>2011-07-21 23:30:09 +0000
committerDan Gohman <gohman@apple.com>2011-07-21 23:30:09 +0000
commite106aee6f5737cd478c98f70bac73f1eb089c46f (patch)
tree9e11844a278024d63737cb26e0a9ebe3f0816fff /llvm/test/Transforms
parentf224ae06d219df331032d197bf9f76b249852762 (diff)
downloadbcm5719-llvm-e106aee6f5737cd478c98f70bac73f1eb089c46f.tar.gz
bcm5719-llvm-e106aee6f5737cd478c98f70bac73f1eb089c46f.zip
Fix MergeInVectorType to check for vector types with the same alloc
size but different element types, so that it filters out the cases that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827. llvm-svn: 135721
Diffstat (limited to 'llvm/test/Transforms')
-rw-r--r--llvm/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll27
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll b/llvm/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll
new file mode 100644
index 00000000000..c3fbdf5f863
--- /dev/null
+++ b/llvm/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll
@@ -0,0 +1,27 @@
+; RUN: opt -scalarrepl -S < %s | FileCheck %s
+; rdar://9786827
+
+; SROA should be able to handle the mixed types and eliminate the allocas here.
+
+; TODO: Currently it does this by falling back to integer "bags of bits".
+; With enough cleverness, it should be possible to convert between <3 x i32>
+; and <2 x i64> by using a combination of a bitcast and a shuffle.
+
+; CHECK: {
+; CHECK-NOT: alloca
+; CHECK: }
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
+target triple = "i386-apple-darwin11.0.0"
+
+define <2 x i64> @foo() nounwind {
+entry:
+ %retval = alloca <3 x i32>, align 16
+ %z = alloca <4 x i32>, align 16
+ %tmp = load <4 x i32>* %z
+ %tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
+ store <3 x i32> %tmp1, <3 x i32>* %retval
+ %0 = bitcast <3 x i32>* %retval to <2 x i64>*
+ %1 = load <2 x i64>* %0, align 1
+ ret <2 x i64> %1
+}
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