[InstCombine] Add test cases to show that we don't propagate 'nsw' flags when converting mul by pow2 constant to shl for splat vectors. NFC

llvm-svn: 306426

1 files changed, 20 insertions, 0 deletions

diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll
index 6e67c7fa08a..ff389a495d3 100644
--- a/llvm/test/Transforms/InstCombine/mul.ll
+++ b/llvm/test/Transforms/InstCombine/mul.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; This test makes sure that mul instructions are properly eliminated.
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
@@ -297,6 +298,15 @@ define i32 @test32(i32 %X) {
 ; CHECK-NEXT: ret i32 %[[shl]]
 }
 
+define <2 x i32> @test32vec(<2 x i32> %X) {
+; CHECK-LABEL: @test32vec(
+; CHECK-NEXT:    [[MUL:%.*]] = shl <2 x i32> [[X:%.*]], <i32 31, i32 31>
+; CHECK-NEXT:    ret <2 x i32> [[MUL]]
+;
+  %mul = mul nsw <2 x i32> %X, <i32 -2147483648, i32 -2147483648>
+  ret <2 x i32> %mul
+}
+
 define i32 @test33(i32 %X) {
 ; CHECK-LABEL: @test33
   %mul = mul nsw i32 %X, 1073741824
@@ -304,3 +314,13 @@ define i32 @test33(i32 %X) {
 ; CHECK-NEXT: ret i32 %[[shl]]
   ret i32 %mul
 }
+
+; TODO: we should propagate nsw flag to the shift here
+define <2 x i32> @test33vec(<2 x i32> %X) {
+; CHECK-LABEL: @test33vec(
+; CHECK-NEXT:    [[MUL:%.*]] = shl <2 x i32> [[X:%.*]], <i32 30, i32 30>
+; CHECK-NEXT:    ret <2 x i32> [[MUL]]
+;
+  %mul = mul nsw <2 x i32> %X, <i32 1073741824, i32 1073741824>
+  ret <2 x i32> %mul
+}