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| author | Craig Topper <craig.topper@gmail.com> | 2016-12-13 07:45:45 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-12-13 07:45:45 +0000 |
| commit | ac75bca1eb169c2d13b88e33440dec3df589f964 (patch) | |
| tree | 3cc4f09b130afc39ef3950698e923dba4a1b0f2f /llvm/test/Transforms | |
| parent | b8ea75a010dac5b14f8d23cb9f7bce0967dee771 (diff) | |
| download | bcm5719-llvm-ac75bca1eb169c2d13b88e33440dec3df589f964.tar.gz bcm5719-llvm-ac75bca1eb169c2d13b88e33440dec3df589f964.zip | |
[X86][InstCombine] Fix SimplifyDemandedVectorElts to handle frcz scalar intrinsics correctly.
Only the lower bits of the input element are used. And only the lower element can be undef since the upper bits are zeroed.
Have InstCombineCalls call SimplifyDemandedVectorElts for these intrinsics to reuse this support.
llvm-svn: 289523
Diffstat (limited to 'llvm/test/Transforms')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/x86-xop.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/x86-xop.ll b/llvm/test/Transforms/InstCombine/x86-xop.ll index d987c757da5..03a3f921abb 100644 --- a/llvm/test/Transforms/InstCombine/x86-xop.ll +++ b/llvm/test/Transforms/InstCombine/x86-xop.ll @@ -1,6 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s +define <2 x double> @test_vfrcz_sd(<2 x double> %a) { +; CHECK-LABEL: @test_vfrcz_sd( +; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %a) +; CHECK-NEXT: ret <2 x double> [[TMP1]] +; + %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1 + %2 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %1) + ret <2 x double> %2 +} + define double @test_vfrcz_sd_0(double %a) { ; CHECK-LABEL: @test_vfrcz_sd_0( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 @@ -26,6 +36,18 @@ define double @test_vfrcz_sd_1(double %a) { ret double %4 } +define <4 x float> @test_vfrcz_ss(<4 x float> %a) { +; CHECK-LABEL: @test_vfrcz_ss( +; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %a) +; CHECK-NEXT: ret <4 x float> [[TMP1]] +; + %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1 + %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 + %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 + %4 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %3) + ret <4 x float> %4 +} + define float @test_vfrcz_ss_0(float %a) { ; CHECK-LABEL: @test_vfrcz_ss_0( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 |
