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| author | Sanjay Patel <spatel@rotateright.com> | 2018-12-03 21:15:17 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-12-03 21:15:17 +0000 |
| commit | 8c655150827b5d56772e628994db08441c554097 (patch) | |
| tree | a3ba34b619e2947c3ca60da932191d5f064b4e84 /llvm/test/Transforms | |
| parent | 660f9c943ff34c3e30708e848407961b462c070d (diff) | |
| download | bcm5719-llvm-8c655150827b5d56772e628994db08441c554097.tar.gz bcm5719-llvm-8c655150827b5d56772e628994db08441c554097.zip | |
[InstCombine] fix undef propagation bug with shuffle+binop
When we have a shuffle that extends a source vector with undefs
and then do some binop on that, we must make sure that the extra
elements remain undef with that binop if we reverse the order of
the binop and shuffle.
'or' is probably the easiest example to show the bug because
'or C, undef --> -1' (not undef). But there are other
opcode/constant combinations where this is true as shown by
the 'shl' test.
llvm-svn: 348191
Diffstat (limited to 'llvm/test/Transforms')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vec_shuffle.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle.ll b/llvm/test/Transforms/InstCombine/vec_shuffle.ll index 6e500451828..b82c8117eeb 100644 --- a/llvm/test/Transforms/InstCombine/vec_shuffle.ll +++ b/llvm/test/Transforms/InstCombine/vec_shuffle.ll @@ -633,13 +633,13 @@ define <4 x i16> @widening_shuffle_shl_constant_op1(<2 x i16> %v) { ret <4 x i16> %bo } -; FIXME: A binop that does not produce undef in the high lanes can not be moved before the shuffle. +; A binop that does not produce undef in the high lanes can not be moved before the shuffle. ; This is not ok because 'shl undef, 1 (or 2)' --> 0' but moving the shuffle results in undef instead. define <4 x i16> @widening_shuffle_shl_constant_op1_non0(<2 x i16> %v) { ; CHECK-LABEL: @widening_shuffle_shl_constant_op1_non0( -; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i16> [[V:%.*]], <i16 2, i16 4> -; CHECK-NEXT: [[BO:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> +; CHECK-NEXT: [[BO:%.*]] = shl <4 x i16> [[SHUF]], <i16 2, i16 4, i16 1, i16 2> ; CHECK-NEXT: ret <4 x i16> [[BO]] ; %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> @@ -647,13 +647,13 @@ define <4 x i16> @widening_shuffle_shl_constant_op1_non0(<2 x i16> %v) { ret <4 x i16> %bo } -; FIXME: A binop that does not produce undef in the high lanes can not be moved before the shuffle. +; A binop that does not produce undef in the high lanes can not be moved before the shuffle. ; This is not ok because 'or -1, undef --> -1' but moving the shuffle results in undef instead. define <4 x i16> @widening_shuffle_or(<2 x i16> %v) { ; CHECK-LABEL: @widening_shuffle_or( -; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i16> [[V:%.*]], <i16 42, i16 -42> -; CHECK-NEXT: [[BO:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> +; CHECK-NEXT: [[BO:%.*]] = or <4 x i16> [[SHUF]], <i16 42, i16 -42, i16 -1, i16 -1> ; CHECK-NEXT: ret <4 x i16> [[BO]] ; %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> |
