AArch64/ARM64: move ARM64 into AArch64's place

This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

llvm-svn: 209577

15 files changed, 14 insertions, 20 deletions

diff --git a/llvm/test/Transforms/ConstantHoisting/ARM64/const-addr.ll b/llvm/test/Transforms/ConstantHoisting/AArch64/const-addr.ll
index 89d596055c4..89d596055c4 100644
--- a/llvm/test/Transforms/ConstantHoisting/ARM64/const-addr.ll
+++ b/llvm/test/Transforms/ConstantHoisting/AArch64/const-addr.ll
diff --git a/llvm/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll b/llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll
index 575be791d9b..575be791d9b 100644
--- a/llvm/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll
+++ b/llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll
diff --git a/llvm/test/Transforms/ConstantHoisting/ARM64/lit.local.cfg b/llvm/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg
index 84ac9811f01..c42034979fc 100644
--- a/llvm/test/Transforms/ConstantHoisting/ARM64/lit.local.cfg
+++ b/llvm/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg
@@ -1,3 +1,3 @@
 targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
     config.unsupported = True
diff --git a/llvm/test/Transforms/GlobalMerge/ARM64/arm64.ll b/llvm/test/Transforms/GlobalMerge/AArch64/arm64.ll
index eea474a74f1..eea474a74f1 100644
--- a/llvm/test/Transforms/GlobalMerge/ARM64/arm64.ll
+++ b/llvm/test/Transforms/GlobalMerge/AArch64/arm64.ll
diff --git a/llvm/test/Transforms/GlobalMerge/ARM64/lit.local.cfg b/llvm/test/Transforms/GlobalMerge/AArch64/lit.local.cfg
index a75a42b6f74..9a66a00189e 100644
--- a/llvm/test/Transforms/GlobalMerge/ARM64/lit.local.cfg
+++ b/llvm/test/Transforms/GlobalMerge/AArch64/lit.local.cfg
@@ -1,4 +1,4 @@
 targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
     config.unsupported = True
 
diff --git a/llvm/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll b/llvm/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
index 1883a8fc8e6..39408a2d394 100644
--- a/llvm/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
@@ -68,7 +68,7 @@ declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind rea
 
 define <4 x i32> @mulByZeroARM64(<4 x i16> %x) nounwind readnone ssp {
 entry:
-  %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
+  %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
   ret <4 x i32> %a
 ; CHECK: entry:
 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
@@ -76,7 +76,7 @@ entry:
 
 define <4 x i32> @mulByOneARM64(<4 x i16> %x) nounwind readnone ssp {
 entry:
-  %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+  %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
   ret <4 x i32> %a
 ; CHECK: entry:
 ; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32>
@@ -85,7 +85,7 @@ entry:
 
 define <4 x i32> @constantMulARM64() nounwind readnone ssp {
 entry:
-  %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
+  %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
   ret <4 x i32> %a
 ; CHECK: entry:
 ; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6>
@@ -93,7 +93,7 @@ entry:
 
 define <4 x i32> @constantMulSARM64() nounwind readnone ssp {
 entry:
-  %b = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+  %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
   ret <4 x i32> %b
 ; CHECK: entry:
 ; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -101,7 +101,7 @@ entry:
 
 define <4 x i32> @constantMulUARM64() nounwind readnone ssp {
 entry:
-  %b = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+  %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
   ret <4 x i32> %b
 ; CHECK: entry:
 ; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -109,17 +109,17 @@ entry:
 
 define <4 x i32> @complex1ARM64(<4 x i16> %x) nounwind readnone ssp {
 entry:
-  %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
+  %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
   %b = add <4 x i32> zeroinitializer, %a
   ret <4 x i32> %b
 ; CHECK: entry:
-; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
+; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
 ; CHECK-NEXT: ret <4 x i32> %a
 }
 
 define <4 x i32> @complex2ARM64(<4 x i32> %x) nounwind readnone ssp {
 entry:
-  %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
+  %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
   %b = add <4 x i32> %x, %a
   ret <4 x i32> %b
 ; CHECK: entry:
@@ -127,8 +127,8 @@ entry:
 ; CHECK-NEXT: ret <4 x i32> %b
 }
 
-declare <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
 
 ; CHECK: attributes #0 = { nounwind readnone ssp }
 ; CHECK: attributes #1 = { nounwind readnone }
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg
index a49957999f0..6642d287068 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg
@@ -1,5 +1,5 @@
 config.suffixes = ['.ll']
 
 targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
     config.unsupported = True
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
index 9a175ad8d35..9a175ad8d35 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll
index 10b2c3a403c..10b2c3a403c 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll
index 217896e55c6..217896e55c6 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll
diff --git a/llvm/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
index f8eb3ed1f35..f8eb3ed1f35 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
diff --git a/llvm/test/Transforms/LoopVectorize/ARM64/gather-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
index bb285382e53..bb285382e53 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM64/gather-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
diff --git a/llvm/test/Transforms/LoopVectorize/ARM64/lit.local.cfg b/llvm/test/Transforms/LoopVectorize/ARM64/lit.local.cfg
deleted file mode 100644
index f1d1f88cf39..00000000000
--- a/llvm/test/Transforms/LoopVectorize/ARM64/lit.local.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-config.suffixes = ['.ll']
-
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
-    config.unsupported = True
-
diff --git a/llvm/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg b/llvm/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg
index 84ac9811f01..c42034979fc 100644
--- a/llvm/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg
@@ -1,3 +1,3 @@
 targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
     config.unsupported = True
diff --git a/llvm/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll
index 3d6da124fc4..3d6da124fc4 100644
--- a/llvm/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll