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authorMatthew Simpson <mssimpso@codeaurora.org>2016-12-16 16:52:35 +0000
committerMatthew Simpson <mssimpso@codeaurora.org>2016-12-16 16:52:35 +0000
commit099af810de82cb7502319ea03e68883be516b5e0 (patch)
tree1734bebadf17909862338d4a2c22387af685c0a5 /llvm/test/Transforms
parent27978005955754bf11b71766c08b768e9fb5c040 (diff)
downloadbcm5719-llvm-099af810de82cb7502319ea03e68883be516b5e0.tar.gz
bcm5719-llvm-099af810de82cb7502319ea03e68883be516b5e0.zip
[LV] Don't attempt to type-shrink scalarized instructions
After r288909, instructions feeding predicated instructions may be scalarized if profitable. Since these instructions will remain scalar, we shouldn't attempt to type-shrink them. We should only truncate vector types to their minimal bit widths. This bug was exposed by enabling the vectorization of loops containing conditional stores by default. llvm-svn: 289958
Diffstat (limited to 'llvm/test/Transforms')
-rw-r--r--llvm/test/Transforms/LoopVectorize/if-pred-stores.ll53
1 files changed, 53 insertions, 0 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll b/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
index 39123756f50..c29af06f672 100644
--- a/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
+++ b/llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
@@ -131,3 +131,56 @@ for.inc26:
%iNewChunks.1.lcssa = phi i32 [ undef, %for.body9 ], [ %iNewChunks.2, %for.inc23 ]
unreachable
}
+
+; VEC-LABEL: @minimal_bit_widths(
+;
+; In the test below, it's more profitable for the expression feeding the
+; conditional store to remain scalar. Since we can only type-shrink vector
+; types, we shouldn't try to represent the expression in a smaller type.
+;
+; VEC: vector.body:
+; VEC: %wide.load = load <2 x i8>, <2 x i8>* {{.*}}, align 1
+; VEC: br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]]
+; VEC: [[IF0]]:
+; VEC: %[[E0:.+]] = extractelement <2 x i8> %wide.load, i32 0
+; VEC: %[[Z0:.+]] = zext i8 %[[E0]] to i32
+; VEC: %[[T0:.+]] = trunc i32 %[[Z0]] to i8
+; VEC: store i8 %[[T0]], i8* {{.*}}, align 1
+; VEC: br label %[[CONT0]]
+; VEC: [[CONT0]]:
+; VEC: br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]]
+; VEC: [[IF1]]:
+; VEC: %[[E1:.+]] = extractelement <2 x i8> %wide.load, i32 1
+; VEC: %[[Z1:.+]] = zext i8 %[[E1]] to i32
+; VEC: %[[T1:.+]] = trunc i32 %[[Z1]] to i8
+; VEC: store i8 %[[T1]], i8* {{.*}}, align 1
+; VEC: br label %[[CONT1]]
+; VEC: [[CONT1]]:
+; VEC: br i1 {{.*}}, label %middle.block, label %vector.body
+;
+define void @minimal_bit_widths(i1 %c) {
+entry:
+ br label %for.body
+
+for.body:
+ %tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ]
+ %tmp1 = phi i64 [ %tmp7, %for.inc ], [ undef, %entry ]
+ %tmp2 = getelementptr i8, i8* undef, i64 %tmp0
+ %tmp3 = load i8, i8* %tmp2, align 1
+ br i1 %c, label %if.then, label %for.inc
+
+if.then:
+ %tmp4 = zext i8 %tmp3 to i32
+ %tmp5 = trunc i32 %tmp4 to i8
+ store i8 %tmp5, i8* %tmp2, align 1
+ br label %for.inc
+
+for.inc:
+ %tmp6 = add nuw nsw i64 %tmp0, 1
+ %tmp7 = add i64 %tmp1, -1
+ %tmp8 = icmp eq i64 %tmp7, 0
+ br i1 %tmp8, label %for.end, label %for.body
+
+for.end:
+ ret void
+}
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