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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-19 18:29:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-19 18:29:07 +0000 |
| commit | d3406bc45c55a2e019cb30b31a7a7e5e6e0b9928 (patch) | |
| tree | 75faa5e204d2da74e1e0f9a800df0baecdcb307f /llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll | |
| parent | 5945447d84320a8361be006e63dc942862adac63 (diff) | |
| download | bcm5719-llvm-d3406bc45c55a2e019cb30b31a7a7e5e6e0b9928.tar.gz bcm5719-llvm-d3406bc45c55a2e019cb30b31a7a7e5e6e0b9928.zip | |
StructurizeCFG: Directly invert cmp instructions
The most common case for a branch condition is
a single use compare. Directly invert the branch
predicate rather than adding a lot of xor i1 true
which the DAG will have to fold later.
This produces nicer to read structurizer output.
This produces some random changes in codegen
due to the DAG swapping branch conditions itself,
and then does a poor job of dealing with those
inverts.
llvm-svn: 300732
Diffstat (limited to 'llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll')
| -rw-r--r-- | llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll b/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll index 668a1e99d81..aff59642cbc 100644 --- a/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll +++ b/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll @@ -11,8 +11,8 @@ bb: bb3: ; preds = %bb7, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ] %tmp4 = fcmp ult float %arg1, 3.500000e+00 -; CHECK: %0 = xor i1 %tmp4, true -; CHECK: br i1 %0, label %bb5, label %Flow +; CHECK: %tmp4 = fcmp oge float %arg1, 3.500000e+00 +; CHECK: br i1 %tmp4, label %bb5, label %Flow br i1 %tmp4, label %bb7, label %bb5 ; CHECK: bb5: @@ -22,7 +22,8 @@ bb5: ; preds = %bb3 br i1 %tmp6, label %bb10, label %bb7 ; CHECK: Flow: -; CHECK: br i1 %3, label %bb7, label %Flow1 +; CHECK: %1 = phi i1 [ %tmp6, %bb5 ], [ %tmp4, %bb3 ] +; CHECK-NEXT: br i1 %1, label %bb7, label %Flow1 ; CHECK: bb7 bb7: ; preds = %bb5, %bb3 @@ -32,9 +33,10 @@ bb7: ; preds = %bb5, %bb3 br i1 %tmp9, label %bb3, label %bb10 ; CHECK: Flow1: -; CHECK: br i1 %7, label %bb10, label %bb3 +; CHECK: %4 = phi i1 [ %tmp9, %bb7 ], [ true, %Flow ] +; CHECK-NEXT: br i1 %4, label %bb10, label %bb3 -; CHECK: bb10 +; CHECK: bb10: bb10: ; preds = %bb7, %bb5 %tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ] store i32 %tmp11, i32 addrspace(1)* %arg, align 4 |
