Move "atomic" and "volatile" designations on instructions after the opcode

of the instruction.

Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.

llvm-svn: 137527

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll b/llvm/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
index 7bca5f5afa0..ebf4f171a3d 100644
--- a/llvm/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
+++ b/llvm/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
@@ -11,14 +11,14 @@ entry:
         br i1 %0, label %bb, label %return
 
 bb:             ; preds = %entry
-        %1 = volatile load i32* null
+        %1 = load volatile i32* null
         unreachable
         
         br label %return
 return:         ; preds = %entry
         ret void
 ; CHECK: @test1
-; CHECK: volatile load
+; CHECK: load volatile
 }
 
 ; rdar://7958343
@@ -35,10 +35,10 @@ entry:
 ; PR7369
 define void @test3() nounwind {
 entry:
-        volatile store i32 4, i32* null
+        store volatile i32 4, i32* null
         ret void
 
 ; CHECK: @test3
-; CHECK: volatile store i32 4, i32* null
+; CHECK: store volatile i32 4, i32* null
 ; CHECK: ret
 }