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| author | Evan Cheng <evan.cheng@apple.com> | 2011-01-29 01:29:26 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-01-29 01:29:26 +0000 |
| commit | d4eff314760090c196bf90ea7d750f322ed849da (patch) | |
| tree | e92b621185fb15a1b604af0a3172906e6c8a04aa /llvm/test/Transforms/SimplifyCFG/switch_create.ll | |
| parent | 74d53758c5d48dcfcf9447f72e809b6765ab1935 (diff) | |
| download | bcm5719-llvm-d4eff314760090c196bf90ea7d750f322ed849da.tar.gz bcm5719-llvm-d4eff314760090c196bf90ea7d750f322ed849da.zip | |
Re-commit r124462 with fixes. Tail recursion elim will now dup ret into unconditional predecessor to enable TCE on demand.
llvm-svn: 124518
Diffstat (limited to 'llvm/test/Transforms/SimplifyCFG/switch_create.ll')
| -rw-r--r-- | llvm/test/Transforms/SimplifyCFG/switch_create.ll | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/llvm/test/Transforms/SimplifyCFG/switch_create.ll b/llvm/test/Transforms/SimplifyCFG/switch_create.ll index da7f65a6ca3..4e199bc8596 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch_create.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch_create.ll @@ -147,7 +147,7 @@ UnifiedReturnBlock: ; preds = %shortcirc_done.4, %shortcirc_next.4 ; CHECK: i32 16, label %UnifiedReturnBlock ; CHECK: i32 17, label %UnifiedReturnBlock ; CHECK: i32 18, label %UnifiedReturnBlock -; CHECK: i32 19, label %switch.edge +; CHECK: i32 19, label %UnifiedReturnBlock ; CHECK: ] } @@ -441,3 +441,29 @@ if.end: ; CHECK-NOT: switch ; CHECK: ret void } + +; PR8675 +; rdar://5134905 +define zeroext i1 @test16(i32 %x) nounwind { +entry: +; CHECK: @test16 +; CHECK: switch i32 %x, label %lor.rhs [ +; CHECK: i32 1, label %lor.end +; CHECK: i32 2, label %lor.end +; CHECK: i32 3, label %lor.end +; CHECK: ] + %cmp.i = icmp eq i32 %x, 1 + br i1 %cmp.i, label %lor.end, label %lor.lhs.false + +lor.lhs.false: + %cmp.i2 = icmp eq i32 %x, 2 + br i1 %cmp.i2, label %lor.end, label %lor.rhs + +lor.rhs: + %cmp.i1 = icmp eq i32 %x, 3 + br label %lor.end + +lor.end: + %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp.i1, %lor.rhs ] + ret i1 %0 +} |
