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authorCraig Topper <craig.topper@intel.com>2019-07-31 22:43:08 +0000
committerCraig Topper <craig.topper@intel.com>2019-07-31 22:43:08 +0000
commitb51dc64063e6ef01f457a3e6e8453126302bde10 (patch)
tree425ebfd3adb41fc46e97a9d1681db88244c81a19 /llvm/test/Transforms/ScalarizeMaskedMemIntrin
parentc724215a70038c02efa06695719e4a384ba2ace2 (diff)
downloadbcm5719-llvm-b51dc64063e6ef01f457a3e6e8453126302bde10.tar.gz
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[X86] Add DAG combine to fold any_extend_vector_inreg+truncstore to an extractelement+store
We have custom code that ignores the normal promoting type legalization on less than 128-bit vector types like v4i8 to emit pavgb, paddusb, psubusb since we don't have the equivalent instruction on a larger element type like v4i32. If this operation appears before a store, we can be left with an any_extend_vector_inreg followed by a truncstore after type legalization. When truncstore isn't legal, this will normally be decomposed into shuffles and a non-truncating store. This will then combine away the any_extend_vector_inreg and shuffle leaving just the store. On avx512, truncstore is legal so we don't decompose it and we had no combines to fix it. This patch adds a new DAG combine to detect this case and emit either an extract_store for 64-bit stoers or a extractelement+store for 32 and 16 bit stores. This makes the avx512 codegen match the avx2 codegen for these situations. I'm restricting to only when -x86-experimental-vector-widening-legalization is false. When we're widening we're not likely to create this any_extend_inreg+truncstore combination. This means we should be able to remove this code when we flip the default. I would like to flip the default soon, but I need to investigate some performance regressions its causing in our branch that I wasn't seeing on trunk. Differential Revision: https://reviews.llvm.org/D65538 llvm-svn: 367488
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