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| author | Cameron McInally <cameron.mcinally@nyu.edu> | 2019-06-24 19:24:23 +0000 |
|---|---|---|
| committer | Cameron McInally <cameron.mcinally@nyu.edu> | 2019-06-24 19:24:23 +0000 |
| commit | fe3f15cf90015ba185ab6ce82f9686933dc475dc (patch) | |
| tree | f894fad9eaf1f29904de450f1b696e4806ba7ffd /llvm/test/Transforms/SLPVectorizer | |
| parent | 4412d83959f58c0eab10c5f6000022782ac5e91a (diff) | |
| download | bcm5719-llvm-fe3f15cf90015ba185ab6ce82f9686933dc475dc.tar.gz bcm5719-llvm-fe3f15cf90015ba185ab6ce82f9686933dc475dc.zip | |
[SLP] Support unary FNeg vectorization
Differential Revision: https://reviews.llvm.org/D63609
llvm-svn: 364219
Diffstat (limited to 'llvm/test/Transforms/SLPVectorizer')
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/X86/phi3.ll | 6 | ||||
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll | 26 |
2 files changed, 10 insertions, 22 deletions
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll b/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll index 7c8757cd14c..18653d6cf6d 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll @@ -54,13 +54,11 @@ if.end7: ; preds = %if.then6, %if.then, define void @Rf_GReset_unary_fneg() { ; CHECK-LABEL: @Rf_GReset_unary_fneg( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SUB:%.*]] = fneg double undef ; CHECK-NEXT: [[TMP0:%.*]] = load double, double* @d, align 8 -; CHECK-NEXT: [[SUB1:%.*]] = fneg double [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double [[TMP0]], i32 1 +; CHECK-NEXT: [[TMP2:%.*]] = fneg <2 x double> [[TMP1]] ; CHECK-NEXT: br i1 icmp eq (%struct.GPar.0.16.26* (...)* inttoptr (i64 115 to %struct.GPar.0.16.26* (...)*), %struct.GPar.0.16.26* (...)* @Rf_gpptr), label [[IF_THEN:%.*]], label [[IF_END7:%.*]] ; CHECK: if.then: -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double [[SUB]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[SUB1]], i32 1 ; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> [[TMP2]], undef ; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP3]], undef ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll b/llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll index f01b9fe4375..722d6f8f809 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll @@ -559,15 +559,10 @@ define void @fcmp_fast_unary_fneg(double* %x) #1 { ; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[IDX1]] to <2 x double>* ; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 8 ; CHECK-NEXT: [[TMP3:%.*]] = fcmp fast oge <2 x double> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP2]], i32 0 -; CHECK-NEXT: [[SUB1:%.*]] = fneg fast double [[TMP4]] -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP2]], i32 1 -; CHECK-NEXT: [[SUB2:%.*]] = fneg fast double [[TMP5]] -; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> undef, double [[SUB1]], i32 0 -; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[SUB2]], i32 1 -; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP3]], <2 x double> [[TMP2]], <2 x double> [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = bitcast double* [[IDX1]] to <2 x double>* -; CHECK-NEXT: store <2 x double> [[TMP8]], <2 x double>* [[TMP9]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = fneg fast <2 x double> [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = select <2 x i1> [[TMP3]], <2 x double> [[TMP2]], <2 x double> [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = bitcast double* [[IDX1]] to <2 x double>* +; CHECK-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 8 ; CHECK-NEXT: ret void ; %idx1 = getelementptr inbounds double, double* %x, i64 0 @@ -632,15 +627,10 @@ define void @fcmp_no_fast_unary_fneg(double* %x) #1 { ; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[IDX1]] to <2 x double>* ; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 8 ; CHECK-NEXT: [[TMP3:%.*]] = fcmp oge <2 x double> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP2]], i32 0 -; CHECK-NEXT: [[SUB1:%.*]] = fneg double [[TMP4]] -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP2]], i32 1 -; CHECK-NEXT: [[SUB2:%.*]] = fneg double [[TMP5]] -; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> undef, double [[SUB1]], i32 0 -; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[SUB2]], i32 1 -; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP3]], <2 x double> [[TMP2]], <2 x double> [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = bitcast double* [[IDX1]] to <2 x double>* -; CHECK-NEXT: store <2 x double> [[TMP8]], <2 x double>* [[TMP9]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = fneg <2 x double> [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = select <2 x i1> [[TMP3]], <2 x double> [[TMP2]], <2 x double> [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = bitcast double* [[IDX1]] to <2 x double>* +; CHECK-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 8 ; CHECK-NEXT: ret void ; %idx1 = getelementptr inbounds double, double* %x, i64 0 |
