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| author | Sanjay Patel <spatel@rotateright.com> | 2014-09-03 17:40:30 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2014-09-03 17:40:30 +0000 |
| commit | 9433a28845dd2fa6953dfd44172c3986f6d9c664 (patch) | |
| tree | d94b186e1c5991a343285eaa9148fff045a9d987 /llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll | |
| parent | efde5a77406a96197249bdaa2d088f687dd26b69 (diff) | |
| download | bcm5719-llvm-9433a28845dd2fa6953dfd44172c3986f6d9c664.tar.gz bcm5719-llvm-9433a28845dd2fa6953dfd44172c3986f6d9c664.zip | |
Preserve IR flags (nsw, nuw, exact, fast-math) in SLP vectorizer (PR20802).
The SLP vectorizer should propagate IR-level optimization hints/flags (nsw, nuw, exact, fast-math)
when converting scalar instructions into vectors. But this isn't a simple copy - we need to take
the intersection (the logical 'and') of the sets of flags on the scalars.
The solution is further complicated because we can have non-uniform (non-SIMD) vector ops after:
http://reviews.llvm.org/D4015
http://llvm.org/viewvc/llvm-project?view=revision&revision=211339
The vast majority of changed files are existing tests that were not propagating IR flags, but I've
also added a new test file for focused testing of IR flag possibilities.
Differential Revision: http://reviews.llvm.org/D5172
llvm-svn: 217051
Diffstat (limited to 'llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll')
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll b/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll index 2ff32739439..3b3bd804e05 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll @@ -6,7 +6,7 @@ target triple = "x86_64-apple-macosx10.9.0" ;CHECK-LABEL: @foo ;CHECK: load <4 x i32> ;CHECK: load <4 x i32> -;CHECK: %[[S1:.+]] = add <4 x i32> +;CHECK: %[[S1:.+]] = add nsw <4 x i32> ;CHECK-DAG: store <4 x i32> %[[S1]] ;CHECK-DAG: %[[A1:.+]] = add nsw i32 ;CHECK-DAG: %[[A2:.+]] = add nsw i32 %[[A1]] |
