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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-25 15:53:55 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-25 15:53:55 +0000 |
| commit | ff3abef395097f7c068dac6feae42c53b7d1e26e (patch) | |
| tree | 6c5d87814a8fa6dc5248b4eabdef19b0c88a494f /llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll | |
| parent | ae3fefe3978237a8b71a6a08a11caab4485b87a4 (diff) | |
| download | bcm5719-llvm-ff3abef395097f7c068dac6feae42c53b7d1e26e.tar.gz bcm5719-llvm-ff3abef395097f7c068dac6feae42c53b7d1e26e.zip | |
[SLPVectorizer] reorderInputsAccordingToOpcode - remove non-Instruction canonicalization
Remove attempts to commute non-Instructions to the LHS - the codegen changes appear to rely on chance more than anything else and also have a tendency to fight existing instcombine canonicalization which moves constants to the RHS of commutable binary ops.
This is prep work towards:
(a) reusing reorderInputsAccordingToOpcode for alt-shuffles and removing the similar reorderAltShuffleOperands
(b) improving reordering to optimized cases with commutable and non-commutable instructions to still find splat/consecutive ops.
Differential Revision: https://reviews.llvm.org/D59738
llvm-svn: 356913
Diffstat (limited to 'llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll')
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll index e8a83fa4b7a..712ff040a91 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll @@ -14,7 +14,7 @@ define void @test() #0 { ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[TMP0]], i32 1 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[TMP0]], i32 2 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP3]], i64 [[TMP0]], i32 3 -; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i64> <i64 3, i64 2, i64 1, i64 0>, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i64> [[TMP4]], <i64 3, i64 2, i64 1, i64 0> ; CHECK-NEXT: [[TMP6]] = extractelement <4 x i64> [[TMP5]], i32 3 ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[TMP5]], i32 0 ; CHECK-NEXT: [[DUMMY_SHL:%.*]] = shl i64 [[TMP7]], 32 |
