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| author | Sanjay Patel <spatel@rotateright.com> | 2014-09-03 17:40:30 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2014-09-03 17:40:30 +0000 |
| commit | 9433a28845dd2fa6953dfd44172c3986f6d9c664 (patch) | |
| tree | d94b186e1c5991a343285eaa9148fff045a9d987 /llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll | |
| parent | efde5a77406a96197249bdaa2d088f687dd26b69 (diff) | |
| download | bcm5719-llvm-9433a28845dd2fa6953dfd44172c3986f6d9c664.tar.gz bcm5719-llvm-9433a28845dd2fa6953dfd44172c3986f6d9c664.zip | |
Preserve IR flags (nsw, nuw, exact, fast-math) in SLP vectorizer (PR20802).
The SLP vectorizer should propagate IR-level optimization hints/flags (nsw, nuw, exact, fast-math)
when converting scalar instructions into vectors. But this isn't a simple copy - we need to take
the intersection (the logical 'and') of the sets of flags on the scalars.
The solution is further complicated because we can have non-uniform (non-SIMD) vector ops after:
http://reviews.llvm.org/D4015
http://llvm.org/viewvc/llvm-project?view=revision&revision=211339
The vast majority of changed files are existing tests that were not propagating IR flags, but I've
also added a new test file for focused testing of IR flag possibilities.
Differential Revision: http://reviews.llvm.org/D5172
llvm-svn: 217051
Diffstat (limited to 'llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll')
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll b/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll index e0c75b147f6..899cfb1f82c 100644 --- a/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll +++ b/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll @@ -5,11 +5,11 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- %class.Complex = type { double, double } ; Code like this is the result of SROA. Make sure we don't vectorize this -; because the in the scalar version of this the shl/or are handled by the +; because the scalar version of the shl/or are handled by the ; backend and disappear, the vectorized code stays. ; CHECK-LABEL: SROAed -; CHECK-NOT: shl <2 x i64> +; CHECK-NOT: shl nuw <2 x i64> ; CHECK-NOT: or <2 x i64> define void @SROAed(%class.Complex* noalias nocapture sret %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) { |
