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| author | Sanjay Patel <spatel@rotateright.com> | 2018-05-01 21:02:09 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-05-01 21:02:09 +0000 |
| commit | d2025a2e311f94b15c12852ae4163cac41e2fd47 (patch) | |
| tree | cc26c4d668f2495835bc8d0f7f5b30631926f913 /llvm/test/Transforms/PhaseOrdering | |
| parent | 52fd16903569c0f8c3ca3dfe89d664969739f2f0 (diff) | |
| download | bcm5719-llvm-d2025a2e311f94b15c12852ae4163cac41e2fd47.tar.gz bcm5719-llvm-d2025a2e311f94b15c12852ae4163cac41e2fd47.zip | |
[AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compare
and (or (lshr X, C), ...), 1 --> (X & C') != 0
I initially thought about implementing the minimal pattern in instcombine as mentioned here:
https://bugs.llvm.org/show_bug.cgi?id=37098#c6
...but we need to do better to catch the more general sequence from the motivating test
(more than 2 bits in the compare). And a test-suite run with statistics showed that this
pattern only happened 2 times currently. It would potentially happen more often if
reassociation worked better (D45842), but it's probably still not too frequent?
This is small enough that I didn't see a need to create a whole new class/file within
AggressiveInstCombine. There are likely other relatively small matchers like what was
discussed in D44266 that would slide under foldUnusualPatterns() (name suggestions welcome).
We could potentially also consolidate matchers for ctpop, bswap, etc under here.
Differential Revision: https://reviews.llvm.org/D45986
llvm-svn: 331311
Diffstat (limited to 'llvm/test/Transforms/PhaseOrdering')
| -rw-r--r-- | llvm/test/Transforms/PhaseOrdering/bitfield-bittests.ll | 25 |
1 files changed, 8 insertions, 17 deletions
diff --git a/llvm/test/Transforms/PhaseOrdering/bitfield-bittests.ll b/llvm/test/Transforms/PhaseOrdering/bitfield-bittests.ll index 59bb9457734..fea74d7ee11 100644 --- a/llvm/test/Transforms/PhaseOrdering/bitfield-bittests.ll +++ b/llvm/test/Transforms/PhaseOrdering/bitfield-bittests.ll @@ -18,15 +18,10 @@ target datalayout = "n32" define i32 @allclear(i32 %a) { ; CHECK-LABEL: @allclear( -; CHECK-NEXT: [[BF_LSHR:%.*]] = lshr i32 [[A:%.*]], 1 -; CHECK-NEXT: [[BF_CLEAR1:%.*]] = or i32 [[BF_LSHR]], [[A]] -; CHECK-NEXT: [[BF_LSHR5:%.*]] = lshr i32 [[A]], 2 -; CHECK-NEXT: [[OR2:%.*]] = or i32 [[BF_CLEAR1]], [[BF_LSHR5]] -; CHECK-NEXT: [[BF_LSHR10:%.*]] = lshr i32 [[A]], 3 -; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR2]], [[BF_LSHR10]] -; CHECK-NEXT: [[OR13:%.*]] = and i32 [[OR83]], 1 -; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[OR13]], 1 -; CHECK-NEXT: ret i32 [[TMP1]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 +; CHECK-NEXT: ret i32 [[TMP3]] ; %a.sroa.0.0.trunc = trunc i32 %a to i8 %a.sroa.5.0.shift = lshr i32 %a, 8 @@ -51,14 +46,10 @@ define i32 @allclear(i32 %a) { define i32 @anyset(i32 %a) { ; CHECK-LABEL: @anyset( -; CHECK-NEXT: [[BF_LSHR:%.*]] = lshr i32 [[A:%.*]], 1 -; CHECK-NEXT: [[BF_CLEAR1:%.*]] = or i32 [[BF_LSHR]], [[A]] -; CHECK-NEXT: [[BF_LSHR5:%.*]] = lshr i32 [[A]], 2 -; CHECK-NEXT: [[OR2:%.*]] = or i32 [[BF_CLEAR1]], [[BF_LSHR5]] -; CHECK-NEXT: [[BF_LSHR10:%.*]] = lshr i32 [[A]], 3 -; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR2]], [[BF_LSHR10]] -; CHECK-NEXT: [[OR13:%.*]] = and i32 [[OR83]], 1 -; CHECK-NEXT: ret i32 [[OR13]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 +; CHECK-NEXT: ret i32 [[TMP3]] ; %a.sroa.0.0.trunc = trunc i32 %a to i8 %a.sroa.5.0.shift = lshr i32 %a, 8 |
