summaryrefslogtreecommitdiffstats
path: root/llvm/test/Transforms/LoopVectorize
diff options
context:
space:
mode:
authorSilviu Baranga <silviu.baranga@arm.com>2016-02-15 15:38:17 +0000
committerSilviu Baranga <silviu.baranga@arm.com>2016-02-15 15:38:17 +0000
commitec7063ac7712f82c6ff62c75ffc8ed02db6dbf58 (patch)
treedf77caaa2d41178d5a7fe089058e316955bdd78d /llvm/test/Transforms/LoopVectorize
parent036c08874ae77b96afc3891a947b29114a5f7d27 (diff)
downloadbcm5719-llvm-ec7063ac7712f82c6ff62c75ffc8ed02db6dbf58.tar.gz
bcm5719-llvm-ec7063ac7712f82c6ff62c75ffc8ed02db6dbf58.zip
[LV] Add support for insertelt/extractelt processing during type truncation
Summary: While shrinking types according to the required bits, we can encounter insert/extract element instructions. This will cause us to reach an llvm_unreachable statement. This change adds support for truncating insert/extract element operations, and adds a regression test. Reviewers: jmolloy Subscribers: mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D17078 llvm-svn: 260893
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize')
-rw-r--r--llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll47
1 files changed, 47 insertions, 0 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll b/llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll
new file mode 100644
index 00000000000..ffe8480138d
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll
@@ -0,0 +1,47 @@
+; RUN: opt -S < %s -loop-vectorize -force-vector-width=4 | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+; CHECK-LABEL: test0
+define void @test0(i16* noalias %M3) {
+entry:
+ br label %if.then1165.us
+
+if.then1165.us: ; preds = %if.then1165.us, %entry
+ %indvars.iv1783 = phi i64 [ 0, %entry ], [ %indvars.iv.next1784, %if.then1165.us ]
+ %conv1177.us = zext i16 undef to i32
+ %add1178.us = add nsw i32 %conv1177.us, undef
+ %conv1179.us = trunc i32 %add1178.us to i16
+ %idxprom1181.us = ashr exact i64 undef, 32
+ %arrayidx1185.us = getelementptr inbounds i16, i16* %M3, i64 %idxprom1181.us
+ store i16 %conv1179.us, i16* %arrayidx1185.us, align 2
+ %indvars.iv.next1784 = add nuw nsw i64 %indvars.iv1783, 1
+ %exitcond1785 = icmp eq i64 %indvars.iv.next1784, 16
+ br i1 %exitcond1785, label %for.inc1286.loopexit, label %if.then1165.us
+
+for.inc1286.loopexit: ; preds = %if.then1165.us
+ ret void
+}
+
+; CHECK-LABEL: test1
+define void @test1(i16* noalias %M3) {
+entry:
+ br label %if.then1165.us
+
+if.then1165.us: ; preds = %if.then1165.us, %entry
+ %indvars.iv1783 = phi i64 [ 0, %entry ], [ %indvars.iv.next1784, %if.then1165.us ]
+ %fptr = load i32, i32* undef, align 4
+ %conv1177.us = zext i16 undef to i32
+ %add1178.us = add nsw i32 %conv1177.us, %fptr
+ %conv1179.us = trunc i32 %add1178.us to i16
+ %idxprom1181.us = ashr exact i64 undef, 32
+ %arrayidx1185.us = getelementptr inbounds i16, i16* %M3, i64 %idxprom1181.us
+ store i16 %conv1179.us, i16* %arrayidx1185.us, align 2
+ %indvars.iv.next1784 = add nuw nsw i64 %indvars.iv1783, 1
+ %exitcond1785 = icmp eq i64 %indvars.iv.next1784, 16
+ br i1 %exitcond1785, label %for.inc1286.loopexit, label %if.then1165.us
+
+for.inc1286.loopexit: ; preds = %if.then1165.us
+ ret void
+}
OpenPOWER on IntegriCloud