diff options
| author | Matthew Simpson <mssimpso@codeaurora.org> | 2017-01-09 19:05:29 +0000 |
|---|---|---|
| committer | Matthew Simpson <mssimpso@codeaurora.org> | 2017-01-09 19:05:29 +0000 |
| commit | cf796478e9e96eb158711da40a558c9a652db2aa (patch) | |
| tree | 104553ff7388c81f3d71201cf2dc65b486fee7b3 /llvm/test/Transforms/LoopVectorize | |
| parent | 6dca542b4af6cf9d78ff994135611a5bf7bbff86 (diff) | |
| download | bcm5719-llvm-cf796478e9e96eb158711da40a558c9a652db2aa.tar.gz bcm5719-llvm-cf796478e9e96eb158711da40a558c9a652db2aa.zip | |
[LV] Fix-up external IV users after updating dominator tree
This patch delays the fix-up step for external induction variable users until
after the dominator tree has been properly updated. This should fix PR30742.
The SCEVExpander in InductionDescriptor::transform can generate code in the
wrong location if the dominator tree is not up-to-date. We should work towards
keeping the dominator tree up-to-date throughout the transformation.
Reference: https://llvm.org/bugs/show_bug.cgi?id=30742
Differential Revision: https://reviews.llvm.org/D28168
llvm-svn: 291462
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/iv_outside_user.ll | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll index d536d1023f4..8a44af96e7f 100644 --- a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll +++ b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll @@ -133,3 +133,48 @@ for.end: store i32 %phi2, i32* %p ret i32 %phi } + +; CHECK-LABEL: @PR30742 +; CHECK: min.iters.checked +; CHECK: %[[N_MOD_VF:.+]] = urem i32 %[[T5:.+]], 2 +; CHECK: %[[N_VEC:.+]] = sub i32 %[[T5]], %[[N_MOD_VF]] +; CHECK: middle.block +; CHECK: %[[CMP:.+]] = icmp eq i32 %[[T5]], %[[N_VEC]] +; CHECK: %[[T15:.+]] = add i32 %tmp03, -7 +; CHECK: %[[T16:.+]] = shl i32 %[[N_MOD_VF]], 3 +; CHECK: %[[T17:.+]] = add i32 %[[T15]], %[[T16]] +; CHECK: %[[T18:.+]] = shl i32 {{.*}}, 3 +; CHECK: %ind.escape = sub i32 %[[T17]], %[[T18]] +; CHECK: br i1 %[[CMP]], label %BB3, label %scalar.ph +define void @PR30742() { +BB0: + br label %BB1 + +BB1: + %tmp00 = load i32, i32* undef, align 16 + %tmp01 = sub i32 %tmp00, undef + %tmp02 = icmp slt i32 %tmp01, 1 + %tmp03 = select i1 %tmp02, i32 1, i32 %tmp01 + %tmp04 = add nsw i32 %tmp03, -7 + br label %BB2 + +BB2: + %tmp05 = phi i32 [ %tmp04, %BB1 ], [ %tmp06, %BB2 ] + %tmp06 = add i32 %tmp05, -8 + %tmp07 = icmp sgt i32 %tmp06, 0 + br i1 %tmp07, label %BB2, label %BB3 + +BB3: + %tmp08 = phi i32 [ %tmp05, %BB2 ] + %tmp09 = sub i32 %tmp00, undef + %tmp10 = icmp slt i32 %tmp09, 1 + %tmp11 = select i1 %tmp10, i32 1, i32 %tmp09 + %tmp12 = add nsw i32 %tmp11, -7 + br label %BB4 + +BB4: + %tmp13 = phi i32 [ %tmp12, %BB3 ], [ %tmp14, %BB4 ] + %tmp14 = add i32 %tmp13, -8 + %tmp15 = icmp sgt i32 %tmp14, 0 + br i1 %tmp15, label %BB4, label %BB1 +} |
