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| author | Momchil Velikov <momchil.velikov@arm.com> | 2020-01-09 13:47:52 +0000 |
|---|---|---|
| committer | Momchil Velikov <momchil.velikov@arm.com> | 2020-01-09 14:03:25 +0000 |
| commit | 173b711e83d7b61a46f55eb44f03ea98f69a1dd6 (patch) | |
| tree | 4bd566faed42ae6fede048e4b04713c66d97db31 /llvm/test/Transforms/LoopVectorize | |
| parent | 032a9393a739a1ef8c30979e2493971207c3c397 (diff) | |
| download | bcm5719-llvm-173b711e83d7b61a46f55eb44f03ea98f69a1dd6.tar.gz bcm5719-llvm-173b711e83d7b61a46f55eb44f03ea98f69a1dd6.zip | |
[ARM][MVE] MVE-I should not be disabled by -mfpu=none
Architecturally, it's allowed to have MVE-I without an FPU, thus
-mfpu=none should not disable MVE-I, or moves to/from FP-registers.
This patch removes `+/-fpregs` from features unconditionally added to
target feature list, depending on FPU and moves the logic to Clang
driver, where the negative form (`-fpregs`) is conditionally added to
the target features list for the cases of `-mfloat-abi=soft`, or
`-mfpu=none` without either `+mve` or `+mve.fp`. Only the negative
form is added by the driver, the positive one is derived from other
features in the backend.
Differential Revision: https://reviews.llvm.org/D71843
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll | 2 | ||||
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll index f005845f2db..7195e61c280 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll @@ -84,4 +84,4 @@ exit: ret void } -attributes #0 = { nounwind "min-legal-vector-width"="0" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+fp-armv8d16sp,+fp16,+fpregs,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp" "use-soft-float"="false" } +attributes #0 = { nounwind "min-legal-vector-width"="0" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+fp-armv8d16sp,+fp16,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp" "use-soft-float"="false" } diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll index cb6e1005db1..353e725580a 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll @@ -84,4 +84,4 @@ while.end: ; preds = %while.body, %entry ret void } -attributes #0 = { "target-features"="+armv8.1-m.main,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fpregs,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-crypto,-d32,-fp-armv8,-fp-armv8sp,-neon,-vfp3,-vfp3sp,-vfp4,-vfp4sp" } +attributes #0 = { "target-features"="+armv8.1-m.main,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-crypto,-d32,-fp-armv8,-fp-armv8sp,-neon,-vfp3,-vfp3sp,-vfp4,-vfp4sp" } |
