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| author | Sanjay Patel <spatel@rotateright.com> | 2018-11-12 15:20:14 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-11-12 15:20:14 +0000 |
| commit | 1456fd76144c925958614547ef7cd7569ad73745 (patch) | |
| tree | d707d3b8bb32e2416a9459591e4f3562bd04550d /llvm/test/Transforms/LoopVectorize | |
| parent | 0f4f4806b376827191ecd794c5795a01925dfcac (diff) | |
| download | bcm5719-llvm-1456fd76144c925958614547ef7cd7569ad73745.tar.gz bcm5719-llvm-1456fd76144c925958614547ef7cd7569ad73745.zip | |
[VectorUtils] add funnel-shifts to the list of vectorizable intrinsics
This just identifies the intrinsics as candidates for vectorization.
It does not mean we will attempt to vectorize under normal conditions
(the test file is forcing vectorization).
The cost model must be fixed to show that the transform is profitable
in general.
Allowing vectorization with these intrinsics is required to avoid
potential regressions from canonicalizing to the intrinsics from
generic IR:
https://bugs.llvm.org/show_bug.cgi?id=37417
llvm-svn: 346661
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/intrinsic.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/intrinsic.ll b/llvm/test/Transforms/LoopVectorize/intrinsic.ll index b0ad22198a0..50cdb73ae8e 100644 --- a/llvm/test/Transforms/LoopVectorize/intrinsic.ll +++ b/llvm/test/Transforms/LoopVectorize/intrinsic.ll @@ -1196,7 +1196,7 @@ declare i32 @llvm.fshl.i32 (i32, i32, i32) define void @fshl_i32(i32 %n, i32* noalias %x, i32* noalias %y, i32 %shAmt) { ; CHECK-LABEL: @fshl_i32( -; CHECK-NOT: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) +; CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) ; CHECK: ret void entry: %cmp = icmp sgt i32 %n, 0 @@ -1222,7 +1222,7 @@ declare i32 @llvm.fshr.i32 (i32, i32, i32) define void @fshr_i32(i32 %n, i32* noalias %x, i32* noalias %y, i32 %shAmt) { ; CHECK-LABEL: @fshr_i32( -; CHECK-NOT: call <4 x i32> @llvm.fshr.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) +; CHECK: call <4 x i32> @llvm.fshr.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]], <4 x i32> [[SPLAT:%.*]]) ; CHECK: ret void entry: %cmp = icmp sgt i32 %n, 0 |
