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| author | Gil Rapaport <gil.rapaport@intel.com> | 2019-10-07 17:24:33 +0300 |
|---|---|---|
| committer | Gil Rapaport <gil.rapaport@intel.com> | 2019-11-08 15:25:14 +0200 |
| commit | 11ed1c0239fd51fd2f064311dc7725277ed0a994 (patch) | |
| tree | 1e03c667e18d66f1af25d83d4a00545e79216a40 /llvm/test/Transforms/LoopVectorize | |
| parent | ef459dedcafbdfda630c884f788a6b53ee9ee30c (diff) | |
| download | bcm5719-llvm-11ed1c0239fd51fd2f064311dc7725277ed0a994.tar.gz bcm5719-llvm-11ed1c0239fd51fd2f064311dc7725277ed0a994.zip | |
[LV] Apply sink-after & interleave-groups as VPlan transformations (NFCI)
This recommits 100e797adb433724a17c9b42b6533cd634cb796b (reverted in
009e032634b3bd7fc32071ac2344b12142286477 for failing an assert). While the
root cause was independently reverted in eaff3004019f97c64c88ab76da6b25106b659b30,
this commit includes a LIT to make sure IVDescriptor's SinkAfter logic does not
try to sink branch instructions.
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll index 998f412674b..f86dcd7e2e7 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll @@ -572,3 +572,38 @@ for.body: for.end: ret void } + +; Do not sink branches: While branches are if-converted and do not require +; sinking, instructions with side effects (e.g. loads) conditioned by those +; branches will become users of the condition bit after vectorization and would +; need to be sunk if the loop is vectorized. +define void @do_not_sink_branch(i32 %x, i32* %in, i32* %out, i32 %tc) local_unnamed_addr #0 { +; NO-SINK-AFTER-LABEL: do_not_sink_branch +; NO-SINK-AFTER-NOT: vector.ph: +; NO-SINK-AFTER: } +entry: + %cmp530 = icmp slt i32 0, %tc + br label %for.body4 + +for.body4: ; preds = %cond.end, %entry + %indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %cond.end ] + %cmp534 = phi i1 [ %cmp530, %entry ], [ %cmp5, %cond.end ] + br i1 %cmp534, label %cond.true, label %cond.end + +cond.true: ; preds = %for.body4 + %arrayidx7 = getelementptr inbounds i32, i32* %in, i32 %indvars.iv + %in.val = load i32, i32* %arrayidx7, align 4 + br label %cond.end + +cond.end: ; preds = %for.body4, %cond.true + %cond = phi i32 [ %in.val, %cond.true ], [ 0, %for.body4 ] + %arrayidx8 = getelementptr inbounds i32, i32* %out, i32 %indvars.iv + store i32 %cond, i32* %arrayidx8, align 4 + %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1 + %cmp5 = icmp slt i32 %indvars.iv.next, %tc + %exitcond = icmp eq i32 %indvars.iv.next, %x + br i1 %exitcond, label %for.end12.loopexit, label %for.body4 + +for.end12.loopexit: ; preds = %cond.end + ret void +} |

