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| author | Serge Pavlov <sepavloff@gmail.com> | 2014-05-11 08:46:12 +0000 |
|---|---|---|
| committer | Serge Pavlov <sepavloff@gmail.com> | 2014-05-11 08:46:12 +0000 |
| commit | 9ef66a8266dc52cb60610096ca302c5d82700bf4 (patch) | |
| tree | 5c10e665bad7b4c6a996e81f109d7eccc6ed9bf8 /llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll | |
| parent | 0e3d1cb5d6df971f02960f4d6433faed7c0b1367 (diff) | |
| download | bcm5719-llvm-9ef66a8266dc52cb60610096ca302c5d82700bf4.tar.gz bcm5719-llvm-9ef66a8266dc52cb60610096ca302c5d82700bf4.zip | |
Reorder shuffle and binary operation.
This patch enables transformations:
BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2))
BinOp(shuffle(v1), const1) -> shuffle(BinOp, const2)
They allow to eliminate extra shuffles in some cases.
Differential Revision: http://reviews.llvm.org/D3525
llvm-svn: 208488
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll b/llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll index 0ec8010756d..e53c1206e42 100644 --- a/llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll +++ b/llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll @@ -19,18 +19,13 @@ entry: ; CHECK-LABEL: @t( ; CHECK: vector.body: -; CHECK: load <4 x i32> -; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = shufflevector -; CHECK: load <4 x i32> -; CHECK: [[VAR2:%[a-zA-Z0-9]+]] = shufflevector +; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = load <4 x i32> +; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = load <4 x i32> ; CHECK: [[VAR3:%[a-zA-Z0-9]+]] = add nsw <4 x i32> [[VAR2]], [[VAR1]] -; CHECK: [[VAR4:%[a-zA-Z0-9]+]] = shufflevector <4 x i32> [[VAR3]] -; CHECK: store <4 x i32> [[VAR4]] -; CHECK: load <4 x i32> -; CHECK: [[VAR5:%[a-zA-Z0-9]+]] = shufflevector -; CHECK-NOT: add nsw <4 x i32> [[VAR4]], [[VAR5]] -; CHECK-NOT: add nsw <4 x i32> [[VAR5]], [[VAR4]] -; CHECK: add nsw <4 x i32> [[VAR3]], [[VAR5]] +; CHECK: store <4 x i32> [[VAR3]] +; CHECK: [[VAR4:%[a-zA-Z0-9.]+]] = load <4 x i32> +; CHECK: add nsw <4 x i32> [[VAR3]], [[VAR4]] +; CHECK-NOT: shufflevector for.body: %indvars.iv = phi i64 [ 93, %entry ], [ %indvars.iv.next, %for.body ] |
