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authorPetar Jovanovic <petar.jovanovic@imgtec.com>2017-04-07 13:31:36 +0000
committerPetar Jovanovic <petar.jovanovic@imgtec.com>2017-04-07 13:31:36 +0000
commitbc54eb89ad8f8a972cd49a73ab449676131e8525 (patch)
treece2b736eb84af4b63cea7af860f48794f11caf1a /llvm/test/Transforms/LoopVectorize/bsd_regex.ll
parente5147247b8cea11e06225e1ee27a5ed4af57824f (diff)
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[mips][msa] Fix generation of bm(n)zi and bins[lr]i instructions
We have two cases here, the first one being the following instruction selection from the builtin function: bm(n)zi builtin -> vselect node -> bins[lr]i machine instruction In case of bm(n)zi having an immediate which has either its high or low bits set, a bins[lr] instruction can be selected through the selectVSplatMask[LR] function. The function counts the number of bits set, and that value is being passed to the bins[lr]i instruction as its immediate, which in turn copies immediate modulo the size of the element in bits plus 1 as per specs, where we get the off-by-one-error. The other case is: bins[lr]i -> vselect node -> bsel.v In this case, a bsel.v instruction gets selected with a mask having one bit less set than required. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D30579 llvm-svn: 299768
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize/bsd_regex.ll')
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