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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll b/llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll index a7f636290ba..631361c9d47 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll @@ -17,28 +17,28 @@ entry: br label %for.body for.body: ; preds = %for.body.for.body_crit_edge, %entry - %indvars.iv.reload = load i64* %indvars.iv.reg2mem + %indvars.iv.reload = load i64, i64* %indvars.iv.reg2mem %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.reload - %0 = load i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3 + %0 = load i32, i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3 %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv.reload - %1 = load i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 + %1 = load i32, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 %idxprom3 = sext i32 %1 to i64 %arrayidx4 = getelementptr inbounds i32, i32* %a, i64 %idxprom3 store i32 %0, i32* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !3 %indvars.iv.next = add i64 %indvars.iv.reload, 1 ; A new store without the parallel metadata here: store i64 %indvars.iv.next, i64* %indvars.iv.next.reg2mem - %indvars.iv.next.reload1 = load i64* %indvars.iv.next.reg2mem + %indvars.iv.next.reload1 = load i64, i64* %indvars.iv.next.reg2mem %arrayidx6 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv.next.reload1 - %2 = load i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3 + %2 = load i32, i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3 store i32 %2, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 - %indvars.iv.next.reload = load i64* %indvars.iv.next.reg2mem + %indvars.iv.next.reload = load i64, i64* %indvars.iv.next.reg2mem %lftr.wideiv = trunc i64 %indvars.iv.next.reload to i32 %exitcond = icmp eq i32 %lftr.wideiv, 512 br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge, !llvm.loop !3 for.body.for.body_crit_edge: ; preds = %for.body - %indvars.iv.next.reload2 = load i64* %indvars.iv.next.reg2mem + %indvars.iv.next.reload2 = load i64, i64* %indvars.iv.next.reg2mem store i64 %indvars.iv.next.reload2, i64* %indvars.iv.reg2mem br label %for.body |
