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| author | Matthew Simpson <mssimpso@codeaurora.org> | 2016-09-26 17:08:37 +0000 |
|---|---|---|
| committer | Matthew Simpson <mssimpso@codeaurora.org> | 2016-09-26 17:08:37 +0000 |
| commit | b764aba2aba7465421e33d761df5b94c50a2f415 (patch) | |
| tree | d2e0b6361f98f0776ba2852be5e3a21ead092e88 /llvm/test/Transforms/LoopVectorize/PowerPC | |
| parent | 5fa302cb65dd45743d9b5af26ca21500e8418bf2 (diff) | |
| download | bcm5719-llvm-b764aba2aba7465421e33d761df5b94c50a2f415.tar.gz bcm5719-llvm-b764aba2aba7465421e33d761df5b94c50a2f415.zip | |
[LV] Scalarize instructions marked scalar after vectorization
This patch ensures that we actually scalarize instructions marked scalar after
vectorization. Previously, such instructions may have been vectorized instead.
Differential Revision: https://reviews.llvm.org/D23889
llvm-svn: 282418
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize/PowerPC')
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll | 4 | ||||
| -rw-r--r-- | llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll index cdd5f042350..76864bc4629 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll @@ -1,5 +1,6 @@ ; RUN: opt < %s -loop-vectorize -S | FileCheck %s +; CHECK: vector.body: ; CHECK: fadd ; CHECK-NEXT: fadd ; CHECK-NEXT: fadd @@ -12,9 +13,8 @@ ; CHECK-NEXT: fadd ; CHECK-NEXT: fadd ; CHECK-NEXT: fadd -; CHECK-NEXT: = ; CHECK-NOT: fadd -; CHECK-SAME: > +; CHECK: middle.block target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-ibm-linux-gnu" diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll index 65b3919585e..15aec0d3539 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll @@ -43,7 +43,7 @@ for.end12: ; preds = %for.end, %entry ; CHECK-LABEL: @s173 ; CHECK: load <4 x float>, <4 x float>* -; CHECK: add i64 %index, 16000 +; CHECK: add nsw i64 %index, 16000 ; CHECK: ret i32 0 } |
